targets/de10nano: use CycloneVPLL, remove 50MHz limitation.
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@ -10,6 +10,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import de10nano
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from litex_boards.platforms import de10nano
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from litex.soc.cores.clock import CycloneVPLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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@ -20,7 +21,7 @@ from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, with_sdram=False):
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def __init__(self, platform, sys_clk_freq, with_sdram=False):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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@ -31,38 +32,12 @@ class _CRG(Module):
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platform.add_period_constraint(clk50, 1e9/50e6)
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platform.add_period_constraint(clk50, 1e9/50e6)
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# PLL
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# PLL
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pll_locked = Signal()
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self.submodules.pll = pll = CycloneVPLL(speedgrade="-I7")
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pll_clk_out = Signal(6)
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pll.register_clkin(clk50, 50e6)
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self.specials += \
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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Instance("ALTPLL",
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
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p_BANDWIDTH_TYPE = "AUTO",
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p_CLK0_DIVIDE_BY = 1,
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p_CLK0_DUTY_CYCLE = 50,
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p_CLK0_MULTIPLY_BY = 1,
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p_CLK0_PHASE_SHIFT = "0",
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p_CLK1_DIVIDE_BY = 1,
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p_CLK1_DUTY_CYCLE = 50,
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p_CLK1_MULTIPLY_BY = 1,
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p_CLK1_PHASE_SHIFT = "5000", # 90°
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p_COMPENSATE_CLOCK = "CLK0",
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p_INCLK0_INPUT_FREQUENCY = 20000,
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p_OPERATION_MODE = "NORMAL",
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i_INCLK = clk50,
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o_CLK = pll_clk_out,
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i_ARESET = 0,
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i_CLKENA = 0x3f,
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i_EXTCLKENA = 0xf,
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i_FBIN = 1,
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i_PFDENA = 1,
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i_PLLENA = 1,
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o_LOCKED = pll_locked,
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)
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self.comb += [
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self.cd_sys.clk.eq(pll_clk_out[0]),
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self.cd_sys_ps.clk.eq(pll_clk_out[1]),
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]
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_locked)
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# SDRAM
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if with_sdram:
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if with_sdram:
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
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@ -70,20 +45,18 @@ class _CRG(Module):
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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platform = de10nano.Platform()
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# SoCCore ---------------------------------------------------------------------------------
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# MiSTerSDRAMSoC -----------------------------------------------------------------------------------
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# MiSTerSDRAMSoC -----------------------------------------------------------------------------------
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class MiSTerSDRAMSoC(SoCCore):
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class MiSTerSDRAMSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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platform = de10nano.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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