Merge pull request #245 from racerxdl/feat/MuselabIceSugarPro
muselab_icesugar_pro: initial support
This commit is contained in:
enjoy-digital
GitHub
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Lucas Teske <lucas@teske.com.br>
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# SPDX-License-Identifier: BSD-2-Clause
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# The Muselab IceSugar Pro PCB and IOs have been documented by @wuxx
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# https://github.com/wuxx/icesugar-pro
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from litex.build.generic_platform import *
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from litex.build.lattice import LatticePlatform
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from litex.build.lattice.programmer import EcpDapProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk
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("clk25", 0, Pins("P6"), IOStandard("LVCMOS33")),
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# Led
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("user_led_n", 0, Pins("B11"), IOStandard("LVCMOS33")), # Red
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("user_led_n", 1, Pins("A11"), IOStandard("LVCMOS33")), # Green
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("user_led_n", 2, Pins("A12"), IOStandard("LVCMOS33")), # Blue
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("rgb_led", 0,
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Subsignal("r", Pins("B11")),
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Subsignal("g", Pins("A11")),
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Subsignal("b", Pins("A12")),
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IOStandard("LVCMOS33"),
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),
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# Reset button
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("cpu_reset_n", 0, Pins("L14"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
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# Serial
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("serial", 0, # iCELink
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Subsignal("tx", Pins("B9")),
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Subsignal("rx", Pins("A9")),
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IOStandard("LVCMOS33")
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),
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# SPIFlash (W25Q256JV (32MB))
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("spiflash", 0,
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Subsignal("cs_n", Pins("N8")),
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# https://github.com/m-labs/nmigen-boards/pull/38
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#Subsignal("clk", Pins("")), driven through USRMCLK
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Subsignal("mosi", Pins("T8")),
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Subsignal("miso", Pins("T7")),
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IOStandard("LVCMOS33"),
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),
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# SDRAM (IS42S16160B (32MB))
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("sdram_clock", 0, Pins("R15"), IOStandard("LVCMOS33")),
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("sdram", 0,
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Subsignal("a", Pins(
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"H15 B13 B12 J16 J15 R12 K16 R13",
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"T13 K15 A13 R14 T14")),
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Subsignal("dq", Pins(
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"F16 E15 F15 D14 E16 C15 D16 B15",
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"R16 P16 P15 N16 N14 M16 M15 L15")),
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Subsignal("we_n", Pins("A15")),
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Subsignal("ras_n", Pins("B16")),
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Subsignal("cas_n", Pins("G16")),
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Subsignal("cs_n", Pins("A14")),
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Subsignal("cke", Pins("L16")),
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Subsignal("ba", Pins("G15 B14")),
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Subsignal("dm", Pins("C16 T15")),
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IOStandard("LVCMOS33"),
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Misc("SLEWRATE=FAST")
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),
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# SDCard
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("spisdcard", 0,
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Subsignal("clk", Pins("J12")),
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Subsignal("mosi", Pins("H12"), Misc("PULLMODE=UP")),
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Subsignal("cs_n", Pins("G12"), Misc("PULLMODE=UP")),
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Subsignal("miso", Pins("K12"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33"),
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),
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("sdcard", 0,
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Subsignal("clk", Pins("J12")),
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Subsignal("cmd", Pins("H12"), Misc("PULLMODE=UP")),
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Subsignal("data", Pins("K12 L12 F12 G12"), Misc("PULLMODE=UP")),
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Misc("SLEWRATE=FAST"),
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IOStandard("LVCMOS33")
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),
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# GPDI
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("gpdi", 0,
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Subsignal("clk_p", Pins("E2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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# Subsignal("clk_n", Pins("D3"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data0_p", Pins("G1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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# Subsignal("data0_n", Pins("F1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data1_p", Pins("J1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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# Subsignal("data1_n", Pins("H2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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Subsignal("data2_p", Pins("L1"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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# Subsignal("data2_n", Pins("K2"), IOStandard("LVCMOS33"), Misc("DRIVE=4")),
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),
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]
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# from colorlight_i5.py adapted to icesugar pro
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# https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-pinmap.png
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_connectors = [
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("pmode", "N3 M2 L2 G2 P1 N1 M1 K1"),
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("pmodf", "T6 R5 R4 R3 P7 R6 T4 T3"),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(LatticePlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self, toolchain="trellis"):
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device = "LFE5U-25F-6BG256C"
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io = _io
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connectors = _connectors
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LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
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def create_programmer(self):
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return EcpDapProgrammer()
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def do_finalize(self, fragment):
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LatticePlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Lucas Teske <lucas@teske.com.br>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import sys
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from migen import *
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from litex.build.io import DDROutput
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from litex_boards.platforms import muselab_icesugar_pro
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoECP5HDMIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect.csr import *
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from litedram.modules import IS42S16160
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_video_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
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else:
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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# Clk / Rst
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if not use_internal_osc:
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clk = platform.request("clk25")
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clk_freq = 25e6
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else:
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clk = Signal()
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div = 5
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self.specials += Instance("OSCG",
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p_DIV = div,
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o_OSC = clk)
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clk_freq = 310e6/div
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rst_n = platform.request("cpu_reset_n")
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk, clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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# Video PLL
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if with_video_pll:
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self.submodules.video_pll = video_pll = ECP5PLL()
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self.comb += video_pll.reset.eq(~rst_n | self.rst)
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video_pll.register_clkin(clk, clk_freq)
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi, 40e6, margin=0)
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video_pll.create_clkout(self.cd_hdmi5x, 200e6, margin=0)
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0xd0000000}}
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def __init__(self, sys_clk_freq=60e6, with_led_chaser=True,
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use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
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with_video_framebuffer=False, **kwargs):
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platform = muselab_icesugar_pro.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, int(sys_clk_freq),
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ident = "LiteX SoC on Muselab iCESugar Pro",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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with_video_pll = with_video_terminal or with_video_framebuffer
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_video_pll=with_video_pll, sdram_rate=sdram_rate)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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ledn = platform.request_all("user_led_n")
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self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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self.add_spi_flash(mode="1x", dummy_cycles=8)
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self.add_constant("SPIFLASH_PAGE_SIZE", 256)
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self.add_constant("SPIFLASH_SECTOR_SIZE", 4096)
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# SDR SDRAM --------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = IS42S16160(sys_clk_freq, sdram_rate),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight i5")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
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parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI)")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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use_internal_osc = args.use_internal_osc,
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sdram_rate = args.sdram_rate,
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l2_size = args.l2_size,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**trellis_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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