qmtech_wukong: Add V3 support and minor cleanups.
This commit is contained in:
Florent Kermarrec
parent
9235468ce1
commit
4df2ab98e7
|
|
@ -37,13 +37,36 @@ _io_v2 = [
|
|||
|
||||
# SD-Card.
|
||||
("sdcard", 0,
|
||||
Subsignal("data", Pins("M5 M7 H6 J6")),
|
||||
Subsignal("cmd", Pins("J8")),
|
||||
Subsignal("clk", Pins("L4")),
|
||||
Subsignal("cd", Pins("N6")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
Subsignal("data", Pins("M5 M7 H6 J6")),
|
||||
Subsignal("cmd", Pins("J8")),
|
||||
Subsignal("clk", Pins("L4")),
|
||||
Subsignal("cd", Pins("N6")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
]
|
||||
|
||||
# IOs specific to V3 of the board.
|
||||
_io_v3 = [
|
||||
# Reset (Key1 button).
|
||||
("cpu_reset", 0, Pins("M6"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Clock.
|
||||
("clk50" , 0, Pins("M21"), IOStandard("LVCMOS33")),
|
||||
|
||||
# Leds.
|
||||
("user_led", 0, Pins("G21"), IOStandard("LVCMOS33")),
|
||||
("user_led", 1, Pins("G20"), IOStandard("LVCMOS33")),
|
||||
|
||||
# SD-Card.
|
||||
("sdcard", 0,
|
||||
Subsignal("data", Pins("M5 M7 H6 J6")),
|
||||
Subsignal("cmd", Pins("J8")),
|
||||
Subsignal("clk", Pins("L4")),
|
||||
Subsignal("cd", Pins("N6")),
|
||||
Misc("SLEW=FAST"),
|
||||
IOStandard("LVCMOS33"),
|
||||
),
|
||||
]
|
||||
|
||||
# IO commons to both versions of the board.
|
||||
|
|
@ -110,9 +133,9 @@ _io_common = [
|
|||
|
||||
# GMII Ethernet.
|
||||
("eth_clocks", 0,
|
||||
Subsignal("tx", Pins("M2")),
|
||||
Subsignal("tx", Pins("M2")),
|
||||
Subsignal("gtx", Pins("U1")),
|
||||
Subsignal("rx", Pins("P4")),
|
||||
Subsignal("rx", Pins("P4")),
|
||||
IOStandard("LVCMOS33")
|
||||
),
|
||||
("eth", 0,
|
||||
|
|
@ -150,15 +173,15 @@ _io_common = [
|
|||
# Connectors ---------------------------------------------------------------------------------------
|
||||
|
||||
_connectors = [
|
||||
("j10", "D5 G5 G7 G8 E5 E6 D6 G6"),
|
||||
("j11", "H4 F4 A4 A5 J4 G4 B4 B5"),
|
||||
("j10", " D5 G5 G7 G8 E5 E6 D6 G6"),
|
||||
("j11", " H4 F4 A4 A5 J4 G4 B4 B5"),
|
||||
("j12", "AB26 AC26 AB24 AC24 AA24 AB25 AA22 AA23",
|
||||
" Y25 AA25 W25 Y26 Y22 Y23 W21 Y21",
|
||||
" V26 W26 U25 U26 V24 W24 V23 W23",
|
||||
" V18 W18 U22 V22 U21 V21 T20 U20",
|
||||
" T19 U19"),
|
||||
("jp2", " H21 H22 K21 J21 H26 G26 G25 F25",
|
||||
"G20 G21 F23 E23 E26 D26 E25 D25"),
|
||||
" T19 U19"),
|
||||
("jp2", " H21 H22 K21 J21 H26 G26 G25 F25",
|
||||
" G20 G21 F23 E23 E26 D26 E25 D25"),
|
||||
("jp3", " AF7 AE7 AD8 AC8 AF9 AE9 AD10 AC10",
|
||||
"AA11 AB11 AF11 AE11 AD14 AC14 AF13 AE13",
|
||||
"AD12 AC12"),
|
||||
|
|
@ -201,14 +224,18 @@ class Platform(Xilinx7SeriesPlatform):
|
|||
default_clk_period = 1e9/50e6
|
||||
|
||||
def __init__(self, board_version=1, speedgrade=-2, toolchain="vivado"):
|
||||
io = _io_common
|
||||
# Check Speedgrade.
|
||||
if speedgrade not in [-1,-2]:
|
||||
raise ValueError(f"Speedgrade {speedgrade} unsupported.")
|
||||
if board_version < 2:
|
||||
io.extend(_io_v1)
|
||||
else:
|
||||
io.extend(_io_v2)
|
||||
Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speedgrade), io, _connectors, toolchain=toolchain)
|
||||
# Create IOs and extend to with board's revision specific IOs.
|
||||
io = _io_common
|
||||
io.extend({
|
||||
1 : _io_v1,
|
||||
2 : _io_v2,
|
||||
3 : _io_v3,
|
||||
}[board_version])
|
||||
# Create Platform.
|
||||
Xilinx7SeriesPlatform.__init__(self, f"xc7a100t{speedgrade}fgg676", io, _connectors, toolchain=toolchain)
|
||||
|
||||
self.toolchain.bitstream_commands = \
|
||||
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
|
||||
|
|
@ -217,7 +244,7 @@ class Platform(Xilinx7SeriesPlatform):
|
|||
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
|
||||
|
||||
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
|
||||
if board_version < 2:
|
||||
if board_version == 1:
|
||||
self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")
|
||||
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
|
||||
self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
|
||||
|
|
|
|||
|
|
@ -43,11 +43,11 @@ class _CRG(LiteXModule):
|
|||
|
||||
# Clk/Rst.
|
||||
clk50 = platform.request("clk50")
|
||||
rst = platform.request("cpu_reset")
|
||||
rst_n = platform.request("cpu_reset")
|
||||
|
||||
# Main PLL.
|
||||
self.pll = pll = S7MMCM(speedgrade=speed_grade)
|
||||
self.comb += pll.reset.eq(~rst | self.rst)
|
||||
self.comb += pll.reset.eq(~rst_n | self.rst)
|
||||
pll.register_clkin(clk50, 50e6)
|
||||
pll.create_clkout(self.cd_sys, sys_clk_freq)
|
||||
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
|
||||
|
|
@ -55,7 +55,7 @@ class _CRG(LiteXModule):
|
|||
|
||||
# IDelay PLL.
|
||||
self.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade)
|
||||
self.comb += pll_idelay.reset.eq(~rst | self.rst)
|
||||
self.comb += pll_idelay.reset.eq(~rst_n | self.rst)
|
||||
pll_idelay.register_clkin(clk50, 50e6)
|
||||
pll_idelay.create_clkout(self.cd_idelay, 200e6)
|
||||
pll_idelay.create_clkout(self.cd_clk100, 100e6)
|
||||
|
|
@ -66,7 +66,7 @@ class _CRG(LiteXModule):
|
|||
# Video PLL.
|
||||
if with_video_pll:
|
||||
self.video_pll = video_pll = S7MMCM(speedgrade=speed_grade)
|
||||
self.comb += video_pll.reset.eq(~rst | self.rst)
|
||||
self.comb += video_pll.reset.eq(~rst_n | self.rst)
|
||||
video_pll.register_clkin(clk50, 50e6)
|
||||
video_pll.create_clkout(self.cd_hdmi, pix_clk)
|
||||
video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk)
|
||||
|
|
@ -74,7 +74,7 @@ class _CRG(LiteXModule):
|
|||
# BaseSoC ------------------------------------------------------------------------------------------
|
||||
|
||||
class BaseSoC(SoCCore):
|
||||
def __init__(self, sys_clk_freq=100e6, board_version=1, speedgrade=-2,
|
||||
def __init__(self, sys_clk_freq=125e6, board_version=1, speedgrade=-2,
|
||||
with_ethernet = False,
|
||||
with_etherbone = False,
|
||||
eth_ip = "192.168.1.50",
|
||||
|
|
@ -138,7 +138,7 @@ def main():
|
|||
from litex.build.parser import LiteXArgumentParser
|
||||
parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.")
|
||||
parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.")
|
||||
parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).")
|
||||
parser.add_target_argument("--board-version", default=1, help="Board version (1 , 2 or 3).")
|
||||
parser.add_target_argument("--speedgrade", default=-1, help="FPGA speedgrade (-1 or -2).")
|
||||
ethopts = parser.target_group.add_mutually_exclusive_group()
|
||||
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
|
||||
|
|
@ -167,7 +167,7 @@ def main():
|
|||
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
|
||||
soc.add_spi_sdcard()
|
||||
if args.with_sdcard:
|
||||
if int(args.board_version) < 2:
|
||||
if int(args.board_version) == 1:
|
||||
soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
|
||||
soc.add_sdcard()
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue