qmtech_wukong: Add V3 support and minor cleanups.

litex_boards/platforms/qmtech_wukong.py

@@ -46,6 +46,29 @@ _io_v2 = [
     ),
 ]
 
+# IOs specific to V3 of the board.
+_io_v3 = [
+    # Reset (Key1 button).
+    ("cpu_reset",  0, Pins("M6"),  IOStandard("LVCMOS33")),
+
+    # Clock.
+    ("clk50"   ,   0, Pins("M21"), IOStandard("LVCMOS33")),
+
+    # Leds.
+    ("user_led",   0, Pins("G21"),   IOStandard("LVCMOS33")),
+    ("user_led",   1, Pins("G20"),   IOStandard("LVCMOS33")),
+
+    # SD-Card.
+    ("sdcard", 0,
+        Subsignal("data", Pins("M5 M7 H6 J6")),
+        Subsignal("cmd",  Pins("J8")),
+        Subsignal("clk",  Pins("L4")),
+        Subsignal("cd",   Pins("N6")),
+        Misc("SLEW=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+]
+
 # IO commons to both versions of the board.
 _io_common = [
     # Key0 button (Key1 is used as cpu reset and is version specific).
@@ -201,14 +224,18 @@ class Platform(Xilinx7SeriesPlatform):
     default_clk_period = 1e9/50e6
 
     def __init__(self, board_version=1, speedgrade=-2, toolchain="vivado"):
-        io = _io_common
+        # Check Speedgrade.
         if speedgrade not in [-1,-2]:
             raise ValueError(f"Speedgrade {speedgrade} unsupported.")
-        if board_version < 2:
+        # Create IOs and extend to with board's revision specific IOs.
-            io.extend(_io_v1)
+        io = _io_common
-        else:
+        io.extend({
-            io.extend(_io_v2)
+            1 : _io_v1,
-        Xilinx7SeriesPlatform.__init__(self, "xc7a100t{}fgg676".format(speedgrade), io, _connectors,  toolchain=toolchain)
+            2 : _io_v2,
+            3 : _io_v3,
+        }[board_version])
+        # Create Platform.
+        Xilinx7SeriesPlatform.__init__(self, f"xc7a100t{speedgrade}fgg676", io, _connectors,  toolchain=toolchain)
 
         self.toolchain.bitstream_commands = \
             ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
@@ -217,7 +244,7 @@ class Platform(Xilinx7SeriesPlatform):
             "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 16]")
-        if board_version < 2:
+        if board_version == 1:
             self.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk50_IBUF]")
         self.add_platform_command("set_property CFGBVS VCCO [current_design]")
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")

litex_boards/targets/qmtech_wukong.py

@@ -43,11 +43,11 @@ class _CRG(LiteXModule):
 
         # Clk/Rst.
         clk50 = platform.request("clk50")
-        rst = platform.request("cpu_reset")
+        rst_n = platform.request("cpu_reset")
 
         # Main PLL.
         self.pll = pll = S7MMCM(speedgrade=speed_grade)
-        self.comb += pll.reset.eq(~rst | self.rst)
+        self.comb += pll.reset.eq(~rst_n | self.rst)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
@@ -55,7 +55,7 @@ class _CRG(LiteXModule):
 
         # IDelay PLL.
         self.pll_idelay = pll_idelay = S7PLL(speedgrade=speed_grade)
-        self.comb += pll_idelay.reset.eq(~rst | self.rst)
+        self.comb += pll_idelay.reset.eq(~rst_n | self.rst)
         pll_idelay.register_clkin(clk50, 50e6)
         pll_idelay.create_clkout(self.cd_idelay, 200e6)
         pll_idelay.create_clkout(self.cd_clk100, 100e6)
@@ -66,7 +66,7 @@ class _CRG(LiteXModule):
         # Video PLL.
         if with_video_pll:
             self.video_pll = video_pll = S7MMCM(speedgrade=speed_grade)
-            self.comb += video_pll.reset.eq(~rst | self.rst)
+            self.comb += video_pll.reset.eq(~rst_n | self.rst)
             video_pll.register_clkin(clk50, 50e6)
             video_pll.create_clkout(self.cd_hdmi,   pix_clk)
             video_pll.create_clkout(self.cd_hdmi5x, 5*pix_clk)
@@ -74,7 +74,7 @@ class _CRG(LiteXModule):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=100e6, board_version=1, speedgrade=-2,
+    def __init__(self, sys_clk_freq=125e6, board_version=1, speedgrade=-2,
         with_ethernet          = False,
         with_etherbone         = False,
         eth_ip                 = "192.168.1.50",
@@ -138,7 +138,7 @@ def main():
     from litex.build.parser import LiteXArgumentParser
     parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board.")
     parser.add_target_argument("--sys-clk-freq",    default=100e6, type=float, help="System clock frequency.")
-    parser.add_target_argument("--board-version",   default=1,                 help="Board version (1 or 2).")
+    parser.add_target_argument("--board-version",   default=1,                 help="Board version (1 , 2 or 3).")
     parser.add_target_argument("--speedgrade",      default=-1,                help="FPGA speedgrade (-1 or -2).")
     ethopts = parser.target_group.add_mutually_exclusive_group()
     ethopts.add_argument("--with-ethernet",         action="store_true",       help="Enable Ethernet support.")
@@ -167,7 +167,7 @@ def main():
         soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
         soc.add_spi_sdcard()
     if args.with_sdcard:
-        if int(args.board_version) < 2:
+        if int(args.board_version) == 1:
             soc.platform.add_extension(qmtech_wukong._sdcard_pmod_io)
         soc.add_sdcard()