Merge pull request #398 from Icenowy/a-e115fb

a_e115fb: new board
This commit is contained in:
enjoy-digital 2022-06-15 11:37:36 +02:00 committed by GitHub
commit 4e0e381f47
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 135 additions and 0 deletions

View File

@ -0,0 +1,53 @@
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Icenowy Zheng <uwu@icenowy.me>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk25", 0, Pins("AB11"), IOStandard("3.3-V LVTTL")),
("clk27", 0, Pins("A11"), IOStandard("3.3-V LVTTL")),
# Rst
("cpu_reset_n", 0, Pins("N21"), IOStandard("1.8-V")), # N21
# Serial
("serial", 0,
Subsignal("tx", Pins("V3"), IOStandard("3.3-V LVTTL")), # GPIOs close to voltage selector
Subsignal("rx", Pins("AA1"), IOStandard("3.3-V LVTTL"))
),
# LEDs
("user_led_n", 0, Pins("A5"), IOStandard("3.3-V LVTTL")), # D3
("user_led_n", 1, Pins("B5"), IOStandard("3.3-V LVTTL")), # D4
("user_led_n", 2, Pins("C4"), IOStandard("3.3-V LVTTL")), # D5
("user_led_n", 3, Pins("C3"), IOStandard("3.3-V LVTTL")), # D6
# Buttons
("user_btn_n", 0, Pins("T1"), IOStandard("3.3-V LVTTL")), # K3
("user_btn_n", 1, Pins("N22"), IOStandard("3.3-V LVTTL")), # K4
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE115F23I7", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)

View File

@ -0,0 +1,82 @@
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import a_e115fb
from litex.soc.cores.clock import CycloneIVPLL
from litex.soc.cores.led import LedChaser
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
# Clk / Rst
clk25 = platform.request("clk25")
rst_n = platform.request("cpu_reset_n")
# PLL
self.submodules.pll = pll = CycloneIVPLL(speedgrade="-7")
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True,
**kwargs):
platform = a_e115fb.Platform()
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on A-E115FB", **kwargs)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
ledn = platform.request_all("user_led_n")
self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on A-E115FB")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.build:
builder.build()
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()