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Add FPC-III board support. 

FPC-III is the Free Permutable Computer; details on the board are
available from:

    https://repo.or.cz/fpc-iii.git
This commit is contained in:
Gary Wong 2021-01-28 09:29:48 -07:00
parent 9bd667720d
commit 4e5bb1bf1e
3 changed files with 365 additions and 0 deletions
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168
litex_boards/platforms/fpc_iii.py Normal file
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
import os
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clock
("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
# LEDs
("user_led", 0, Pins("N16"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 1, Pins("P20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 2, Pins("R20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 3, Pins("N20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 4, Pins("U20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 5, Pins("M20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 6, Pins("T20"), IOStandard("LVCMOS15"), Misc( "OPENDRAIN=ON" ) ),
("user_led", 7, Pins("D6"), IOStandard("LVCMOS33"), Misc( "OPENDRAIN=ON" ) ),
# Serial
#("serial", 0,
# Subsignal("rx", Pins("N2"), IOStandard("LVCMOS33")),
# Subsignal("tx", Pins("M1"), IOStandard("LVCMOS33"))),
# USB FIFO
("usb_fifo", 0,
Subsignal( "data", Pins( "N2 M1 M3 L1 L2 K1 K2 J1" ) ),
Subsignal( "rxf_n", Pins( "H1" ) ),
Subsignal( "txe_n", Pins( "H2" ) ),
Subsignal( "rd_n", Pins( "G1" ) ),
Subsignal( "wr_n", Pins( "G2" ) ),
Subsignal( "siwua", Pins( "F1" ) )
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
),
# SDCard
("spisdcard", 0,
Subsignal("clk", Pins("A9")),
Subsignal("mosi", Pins("E9"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("B8"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins("D9"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("clk", Pins("A9")),
Subsignal("cmd", Pins("E9"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("D9 B9 C8 B8"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
# USB ULPI
("ulpi", 0,
Subsignal("clk", Pins("C6")),
Subsignal("stp", Pins("D7")),
Subsignal("dir", Pins("A7")),
Subsignal("nxt", Pins("C7")),
Subsignal("reset", Pins("D8")),
Subsignal("data", Pins("A5 B5 A4 B4 A3 B3 A2 B2")),
IOStandard("LVCMOS33")
),
# DDR3 SDRAM
("dram_vtt_en", 0, Pins( "M19" ), IOStandard( "LVCMOS15" ), Misc( "OPENDRAIN=ON" ) ),
("ddram", 0,
Subsignal( "a", Pins( "E18 H16 D18 L16 H17 E17 G18 C18 "
"G16 D17 J16 F18 J17 F16 F17" ),
IOStandard( "SSTL15_I" ) ),
Subsignal( "ba", Pins( "M18 H18 L17" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "ras_n", Pins( "R17" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "cas_n", Pins( "R16" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "we_n", Pins( "M17" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "cs_n", Pins( "P17" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "dm", Pins( "F20 T18" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "dq", Pins( "J20 F19 J19 E19 K19 E20 K20 G20 ",
"T17 U16 P18 U17 N19 U18 P19 U19" ),
IOStandard( "SSTL15_I" ), Misc( "TERMINATION=50" ) ),
Subsignal( "dqs_p", Pins( "G19 T19" ), IOStandard( "SSTL15D_I" ),
Misc( "TERMINATION=OFF" ), Misc( "DIFFRESISTOR=100" ) ),
Subsignal( "clk_p", Pins( "K16" ), IOStandard( "SSTL15D_I" ) ),
Subsignal( "cke", Pins( "D19" ), IOStandard( "SSTL15_I" ) ),
Subsignal( "odt", Pins( "H4" ) ), # FIXME not connected
Subsignal( "reset_n", Pins( "L20" ), IOStandard( "SSTL15_I" ) ),
# Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see
# FPGA-TN-02035, section 6.7.
Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),
IOStandard( "SSTL15_II" ) ),
Misc( "SLEWRATE=FAST" ) ),
# MII Ethernet
("eth_clocks", 0,
Subsignal("rx", Pins("L5")),
Subsignal("tx", Pins("P1")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rx_data", Pins("N3 N4 N5 P4")),
Subsignal("rx_dv", Pins("M5")),
Subsignal("tx_data", Pins("N1 L4 L3 K4")),
Subsignal("tx_en", Pins("P2")),
Subsignal("mdc", Pins("P5")),
Subsignal("mdio", Pins("J5")),
Subsignal("rx_er", Pins("K5")),
Subsignal("int_n", Pins("M4")),
Subsignal("rst_n", Pins("C9")), # FIXME not connected
IOStandard("LVCMOS33")
),
# HDMI output
("hdmi", 0,
Subsignal( "data0", Pins( "G3" ) ),
Subsignal( "data1", Pins( "F4" ) ),
Subsignal( "data2", Pins( "C1" ) ),
Subsignal( "clk", Pins( "E4" ) ),
IOStandard( "LVCMOS33D" ), Misc( "DRIVE=8 SLEWRATE=FAST" ) ),
# USB host 1
("usbhost", 0,
Subsignal( "dp", Pins( "B6" ) ),
Subsignal( "dn", Pins( "A6" ) ),
IOStandard( "LVCMOS33" ) )
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, toolchain="trellis", **kwargs):
LatticePlatform.__init__(self, "LFE5U-85F-8BG381", _io, _connectors, toolchain=toolchain, **kwargs)
def request(self, *args, **kwargs):
return LatticePlatform.request(self, *args, **kwargs)
def create_programmer(self):
return OpenOCDJTAGProgrammer("openocd_fpc_iii.cfg")
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)

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litex_boards/prog/openocd_fpc_iii.cfg Normal file
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adapter driver ftdi
transport select jtag
# ftdi_device_desc "FPC-III" (once programmed)
ftdi_vid_pid 0x1209 0xFC30 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0xfff8 0xfffb
ftdi_layout_signal LED -ndata 0x10
reset_config none
# default speed
adapter speed 25000
# ECP5 device - LFE5U-85
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41113043

180
litex_boards/targets/fpc_iii.py Executable file
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import fpc_iii
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import IS43TR16256A
from litedram.phy import ECP5DDRPHY
from liteeth.phy.mii import LiteEthPHYMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk25 = platform.request("clk25")
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk25)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout,
),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs):
platform = fpc_iii.Platform(toolchain=toolchain)
if kwargs[ "uart_name" ] == "serial":
kwargs[ "uart_name" ] = "usb_fifo"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on FPC-III",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
ddram = platform.request("ddram")
# Pin K16 (PR29A) is available as the true component of a
# differential pair, and K17 (PR29B) is its complement.
# So the clk_polarity=1 parameter would be necessary only if
# some idiot were laying out the board and wired K16 to
# the DDR3 CK-, and K17 to CK+. The chances of that
# happening are remote, of course.
self.submodules.ddrphy = ECP5DDRPHY( ddram, sys_clk_freq, clk_polarity=1 )
self.ddrphy.settings.rtt_nom = "disabled"
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.comb += ddram.vccio.eq( Replicate( C(1), ddram.vccio.nbits ) )
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = IS43TR16256A(sys_clk_freq, "1:2"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x20000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
self.comb += platform.request("dram_vtt_en").eq( 0 if self.integrated_main_ram_size else 1 )
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=80e6, help="system clock frequency (default=80MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="enable Ethernet wishbone support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
if __name__ == "__main__":
main()