Merge pull request #2 from litex-hub/master

Merge upstream before changes

litex_boards/platforms/ecpix5.py

@@ -17,29 +17,29 @@ _io = [
 
     # Leds
     ("rgb_led", 0,
-        Subsignal("r", Pins("U21")),
-        Subsignal("g", Pins("W21")),
-        Subsignal("b", Pins("T24")),
-        IOStandard("LVCMOS33"),
-    ),
-    ("rgb_led", 1,
-        Subsignal("r", Pins("T23")),
-        Subsignal("g", Pins("R21")),
-        Subsignal("b", Pins("T22")),
-        IOStandard("LVCMOS33"),
-    ),
-    ("rgb_led", 2,
         Subsignal("r", Pins("P21")),
         Subsignal("g", Pins("R23")),
         Subsignal("b", Pins("P22")),
         IOStandard("LVCMOS33"),
     ),
-    ("rgb_led", 3,
+    ("rgb_led", 1,
         Subsignal("r", Pins("K21")),
         Subsignal("g", Pins("K24")),
         Subsignal("b", Pins("M21")),
         IOStandard("LVCMOS33"),
     ),
+    ("rgb_led", 2,
+        Subsignal("r", Pins("U21")),
+        Subsignal("g", Pins("W21")),
+        Subsignal("b", Pins("T24")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("rgb_led", 3,
+        Subsignal("r", Pins("T23")),
+        Subsignal("g", Pins("R21")),
+        Subsignal("b", Pins("T22")),
+        IOStandard("LVCMOS33"),
+    ),
 
     # Serial
     ("serial", 0,
@@ -51,7 +51,7 @@ _io = [
     ("ddram", 0,
         Subsignal("a", Pins(
             "T5 M3 L3 V6 K2 W6 K3 L1",
-            "H2 L2 N1 J1 M1 K1"),
+            "H2 L2 N1 J1 M1 K1 H1"),
             IOStandard("SSTL15_I")),
         Subsignal("ba",    Pins("U6 N3 N4"), IOStandard("SSTL15_I")),
         Subsignal("ras_n", Pins("T3"), IOStandard("SSTL15_I")),

litex_boards/platforms/fpc_iii.py

@@ -0,0 +1,167 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
+
+import os
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clock
+    ("clk25",  0, Pins("P3"), IOStandard("LVCMOS33")),
+
+    # LEDs
+    ("user_led", 0, Pins("N16"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 1, Pins("P20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 2, Pins("R20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 3, Pins("N20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 4, Pins("U20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 5, Pins("M20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 6, Pins("T20"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("user_led", 7, Pins("D6"),  IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
+
+    # USB FIFO
+    ("usb_fifo", 0,
+      Subsignal( "data",  Pins("N2 M1 M3 L1 L2 K1 K2 J1")),
+      Subsignal( "rxf_n", Pins("H1")),
+      Subsignal( "txe_n", Pins("H2")),
+      Subsignal( "rd_n",  Pins("G1")),
+      Subsignal( "wr_n",  Pins("G2")),
+      Subsignal( "siwua", Pins("F1"))
+    ),
+
+    # SPIFlash
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")),
+        Subsignal("wp",   Pins("Y2"), IOStandard("LVCMOS33")),
+        Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("R2"),          IOStandard("LVCMOS33")),
+        Subsignal("dq",   Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
+    ),
+
+    # SDCard
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("A9")),
+        Subsignal("mosi", Pins("E9"), Misc("PULLMODE=UP")),
+        Subsignal("cs_n", Pins("B8"), Misc("PULLMODE=UP")),
+        Subsignal("miso", Pins("D9"), Misc("PULLMODE=UP")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+    ("sdcard", 0,
+        Subsignal("clk",  Pins("A9")),
+        Subsignal("cmd",  Pins("E9"), Misc("PULLMODE=UP")),
+        Subsignal("data", Pins("D9 B9 C8 B8"), Misc("PULLMODE=UP")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+    # USB ULPI
+    ("ulpi", 0,
+        Subsignal("clk",   Pins("C6")),
+        Subsignal("stp",   Pins("D7")),
+        Subsignal("dir",   Pins("A7")),
+        Subsignal("nxt",   Pins("C7")),
+        Subsignal("reset", Pins("D8")),
+        Subsignal("data",  Pins("A5 B5 A4 B4 A3 B3 A2 B2")),
+        IOStandard("LVCMOS33")
+    ),
+
+    # DDR3 SDRAM
+    ("dram_vtt_en", 0, Pins("M19"), IOStandard("LVCMOS15"), Misc("OPENDRAIN=ON")),
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "E18 H16 D18 L16 H17 E17 G18 C18 "
+            "G16 D17 J16 F18 J17 F16 F17"
+        ),
+        IOStandard("SSTL15_I")),
+      Subsignal("ba",    Pins("M18 H18 L17"), IOStandard("SSTL15_I")),
+      Subsignal("ras_n", Pins("R17"), IOStandard("SSTL15_I")),
+      Subsignal("cas_n", Pins("R16"), IOStandard("SSTL15_I")),
+      Subsignal("we_n",  Pins("M17"), IOStandard("SSTL15_I")),
+      Subsignal("cs_n",  Pins("P17"), IOStandard("SSTL15_I")),
+      Subsignal("dm", Pins("F20 T18"), IOStandard("SSTL15_I")),
+      Subsignal("dq", Pins(
+          "J20 F19 J19 E19 K19 E20 K20 G20",
+          "T17 U16 P18 U17 N19 U18 P19 U19"),
+          IOStandard("SSTL15_I"),
+          Misc("TERMINATION=50")),
+      Subsignal("dqs_p", Pins("G19 T19"), IOStandard("SSTL15D_I"),
+          Misc("TERMINATION=OFF"),
+          Misc("DIFFRESISTOR=100")),
+      Subsignal("clk_p"  , Pins("K16"), IOStandard("SSTL15D_I")),
+      Subsignal("cke",     Pins("D19"), IOStandard("SSTL15_I")),
+      #Subsignal("odt",    Pins("")), Not connected.
+      Subsignal("reset_n", Pins("L20"), IOStandard("SSTL15_I")),
+      # Pseudo-VCCIO pads: SSTL15_II for 10 mA drive strength, see FPGA-TN-02035, section 6.7.
+      Subsignal( "vccio", Pins( "C20 E16 J18 K18 L18 L19 N17 N18 T16" ),
+          IOStandard( "SSTL15_II" ) ),
+      Misc("SLEWRATE=FAST")),
+
+    # MII Ethernet
+    ("eth_clocks", 0,
+        Subsignal("rx", Pins("L5")),
+        Subsignal("tx", Pins("P1")),
+        IOStandard("LVCMOS33"),
+    ),
+    ("eth", 0,
+        Subsignal("rx_data", Pins("N3 N4 N5 P4")),
+        Subsignal("rx_dv",   Pins("M5")),
+        Subsignal("tx_data", Pins("N1 L4 L3 K4")),
+        Subsignal("tx_en",   Pins("P2")),
+        Subsignal("mdc",     Pins("P5")),
+        Subsignal("mdio",    Pins("J5")),
+        Subsignal("rx_er",   Pins("K5")),
+        Subsignal("int_n",   Pins("M4")),
+        #Subsignal("rst_n",   Pins("")), # Not connected
+        IOStandard("LVCMOS33")
+    ),
+
+    # HDMI output
+    ("hdmi", 0,
+       Subsignal("data0", Pins("G3")),
+       Subsignal("data1", Pins("F4")),
+       Subsignal("data2", Pins("C1")),
+       Subsignal("clk", Pins("E4") ),
+       IOStandard("LVCMOS33D"),
+       Misc("DRIVE=8 SLEWRATE=FAST")),
+
+    # USB host 1
+    ("usbhost", 0,
+       Subsignal("dp", Pins("B6")),
+       Subsignal("dn", Pins("A6")),
+       IOStandard("LVCMOS33"))
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(LatticePlatform):
+    default_clk_name   = "clk25"
+    default_clk_period = 1e9/25e6
+
+    def __init__(self, toolchain="trellis", **kwargs):
+        LatticePlatform.__init__(self, "LFE5U-85F-8BG381", _io, _connectors, toolchain=toolchain, **kwargs)
+
+    def request(self, *args, **kwargs):
+        return LatticePlatform.request(self, *args, **kwargs)
+
+    def create_programmer(self):
+        return OpenOCDJTAGProgrammer("openocd_fpc_iii.cfg")
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk25",  loose=True), 1e9/25e6)

litex_boards/platforms/netv2.py

@@ -191,9 +191,12 @@ class Platform(XilinxPlatform):
     default_clk_name   = "clk50"
     default_clk_period = 1e9/50e6
 
-    def __init__(self, device="xc7a35t"):
+    def __init__(self, variant="a7-35"):
-        assert device in ["xc7a35t", "xc7a100t"]
+        device = {
-        XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado")
+            "a7-35":  "xc7a35t-fgg484-2",
+            "a7-100": "xc7a100t-fgg484-2"
+        }[variant]
+        XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
 
     def create_programmer(self):
         bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"

litex_boards/platforms/tec0117.py

@@ -46,6 +46,18 @@ _io = [
         Subsignal("miso", Pins("14"), IOStandard("LVCMOS33")),
         Subsignal("mosi", Pins("15"), IOStandard("LVCMOS33")),
     ),
+
+    # SDRAM (embedded in SIP, requires specific IO naming)
+    ("O_sdram_clk",   0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_cke",   0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_cs_n",  0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_we_n",  0, Pins(1), IOStandard("LVCMOS33")),
+    ("O_sdram_dqm",   0, Pins(2), IOStandard("LVCMOS33")),
+    ("O_sdram_addr",  0, Pins(12), IOStandard("LVCMOS33")),
+    ("O_sdram_ba",    0, Pins(2), IOStandard("LVCMOS33")),
+    ("IO_sdram_dq",   0, Pins(16), IOStandard("LVCMOS33")),
 ]
 
 # Connectors ---------------------------------------------------------------------------------------

litex_boards/prog/openocd_fpc_iii.cfg

@@ -0,0 +1,17 @@
+adapter driver ftdi
+transport select jtag
+
+# ftdi_device_desc "FPC-III" (once programmed)
+ftdi_vid_pid 0x1209 0xFC30 0x0403 0x6010
+
+ftdi_channel 0
+
+ftdi_layout_init 0xfff8 0xfffb
+ftdi_layout_signal LED -ndata 0x10
+reset_config none
+
+# default speed
+adapter speed 25000
+
+# ECP5 device - LFE5U-85
+jtag newtap ecp5 tap -irlen 8 -expected-id 0x41113043

litex_boards/targets/ecpix5.py

@@ -20,6 +20,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K256M16
 from litedram.phy import ECP5DDRPHY
@@ -116,11 +117,16 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
-        # Leds (Disable...) ------------------------------------------------------------------------
+        # Leds -------------------------------------------------------------------------------------
+        leds_pads = []
         for i in range(4):
             rgb_led_pads = platform.request("rgb_led", i)
-            for c in "rgb":
+            self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds.
-                self.comb += getattr(rgb_led_pads, c).eq(1)
+            leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
+        self.submodules.leds = LedChaser(
+            pads         = Cat(leds_pads),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
 
 # Build --------------------------------------------------------------------------------------------
 

litex_boards/targets/fpc_iii.py

@@ -0,0 +1,175 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2020 Gary Wong <gtw@gnu.org>
+# SPDX-License-Identifier: BSD-2-Clause
+
+import os
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import fpc_iii
+
+from litex.build.lattice.trellis import trellis_args, trellis_argdict
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+from litedram.modules import IS43TR16256A
+from litedram.phy import ECP5DDRPHY
+
+from liteeth.phy.mii import LiteEthPHYMII
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.rst = Signal()
+        self.clock_domains.cd_init    = ClockDomain()
+        self.clock_domains.cd_por     = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys     = ClockDomain()
+        self.clock_domains.cd_sys2x   = ClockDomain()
+        self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
+
+        self.stop  = Signal()
+        self.reset = Signal()
+
+        # Clk / Rst
+        clk25 = platform.request("clk25")
+
+        # Power on reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(clk25)
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
+        # PLL
+        sys2x_clk_ecsout = Signal()
+        self.submodules.pll = pll = ECP5PLL()
+        self.comb += pll.reset.eq(~por_done | self.rst)
+        pll.register_clkin(clk25, 25e6)
+        pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        pll.create_clkout(self.cd_init, 25e6)
+        self.specials += [
+            Instance("ECLKBRIDGECS",
+                i_CLK0   = self.cd_sys2x_i.clk,
+                i_SEL    = 0,
+                o_ECSOUT = sys2x_clk_ecsout,
+            ),
+            Instance("ECLKSYNCB",
+                i_ECLKI = sys2x_clk_ecsout,
+                i_STOP  = self.stop,
+                o_ECLKO = self.cd_sys2x.clk),
+            Instance("CLKDIVF",
+                p_DIV     = "2.0",
+                i_ALIGNWD = 0,
+                i_CLKI    = self.cd_sys2x.clk,
+                i_RST     = self.reset,
+                o_CDIVX   = self.cd_sys.clk),
+            AsyncResetSynchronizer(self.cd_sys,    ~pll.locked | self.reset),
+            AsyncResetSynchronizer(self.cd_sys2x,  ~pll.locked | self.reset),
+        ]
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(80e6), toolchain="trellis", with_ethernet=False, with_etherbone=False, **kwargs):
+        platform = fpc_iii.Platform(toolchain=toolchain)
+
+        # Serial -----------------------------------------------------------------------------------
+        if kwargs[ "uart_name" ] == "serial":
+            # Defaults to USB FIFO since no real serial.
+            kwargs[ "uart_name" ] = "usb_fifo"
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident          = "LiteX SoC on FPC-III",
+            ident_version  = True,
+            **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            ddram = platform.request("ddram")
+            self.submodules.ddrphy = ECP5DDRPHY(ddram, sys_clk_freq, clk_polarity=1) # clk_p/n swapped.
+            self.ddrphy.settings.rtt_nom = "disabled"
+            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
+            self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
+            self.comb += ddram.vccio.eq(Replicate(C(1), ddram.vccio.nbits))
+            self.add_csr("ddrphy")
+            self.add_sdram("sdram",
+                phy                     = self.ddrphy,
+                module                  = IS43TR16256A(sys_clk_freq, "1:2"),
+                origin                  = self.mem_map["main_ram"],
+                size                    = kwargs.get("max_sdram_size", 0x20000000),
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
+                l2_cache_reverse        = True
+            )
+        self.comb += platform.request("dram_vtt_en").eq(0 if self.integrated_main_ram_size else 1)
+
+        # Ethernet ---------------------------------------------------------------------------------
+        if with_ethernet or with_etherbone:
+            self.submodules.ethphy = LiteEthPHYMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            if with_ethernet:
+                self.add_ethernet(phy=self.ethphy)
+            if with_etherbone:
+                self.add_etherbone(phy=self.ethphy)
+
+        # Leds -------------------------------------------------------------------------------------
+        self.submodules.leds = LedChaser(
+            pads         = platform.request_all("user_led"),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on FPC-III")
+    parser.add_argument("--build",           action="store_true", help="Build bitstream")
+    parser.add_argument("--load",            action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain",       default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",    default=80e6,        help="System clock frequency (default=80MHz)")
+    parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone",  action="store_true", help="Enable Ethernet wishbone support")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    trellis_args(parser)
+    args = parser.parse_args()
+
+    assert not (args.with_ethernet and args.with_etherbone)
+    soc = BaseSoC(
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        with_ethernet = args.with_ethernet,
+        with_etherbone = args.with_etherbone,
+        **soc_sdram_argdict(args))
+    assert not (args.with_spi_sdcard and args.with_sdcard)
+    if args.with_spi_sdcard:
+        soc.add_spi_sdcard()
+    if args.with_sdcard:
+        soc.add_sdcard()
+    builder = Builder(soc, **builder_argdict(args))
+    builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
+    builder.build(**builder_kargs, run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
+
+if __name__ == "__main__":
+    main()

litex_boards/targets/netv2.py

@@ -62,8 +62,8 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs):
+    def __init__(self, variant="a7-35", sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs):
-        platform = netv2.Platform()
+        platform = netv2.Platform(variant=variant)
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -119,6 +119,7 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
     parser.add_argument("--build",           action="store_true", help="Build bitstream")
     parser.add_argument("--load",            action="store_true", help="Load bitstream")
+    parser.add_argument("--variant",         default="a7-35",     help="Board variant: a7-35 (default) or a7-100")
     parser.add_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency (default: 100MHz)")
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-pcie",       action="store_true", help="Enable PCIe support")
@@ -131,6 +132,7 @@ def main():
     args = parser.parse_args()
 
     soc = BaseSoC(
+        variant       = args.variant,
         sys_clk_freq  = int(float(args.sys_clk_freq)),
         with_ethernet = args.with_ethernet,
         with_pcie     = args.with_pcie,

litex_boards/targets/tec0117.py

@@ -22,12 +22,15 @@ from litex.soc.cores.led import LedChaser
 
 from litex_boards.platforms import tec0117
 
+from litedram.modules import M12L64322A  # FIXME
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
+
 kB = 1024
 mB = 1024*kB
 
 class BaseSoC(SoCCore):
     mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
-    def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), with_sdram=False, sdram_rate="1:1", **kwargs):
         platform = tec0117.Platform()
 
         # SoC can have littel a bram, as a treat
@@ -44,10 +47,7 @@ class BaseSoC(SoCCore):
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = CRG(
+        self.submodules.crg = CRG(platform.request("clk12"), ~platform.request("rst"))
-                platform.request(platform.default_clk_name),
-                ~platform.request('rst'),
-        )
 
         # SPI Flash --------------------------------------------------------------------------------
         self.add_spi_flash(mode="1x", dummy_cycles=8)
@@ -59,6 +59,36 @@ class BaseSoC(SoCCore):
             linker = True)
         )
 
+        # SDR SDRAM (WIP) --------------------------------------------------------------------------
+        if with_sdram:
+            class SDRAMPads:
+                def __init__(self):
+                    self.clk   = platform.request("O_sdram_clk")
+                    self.cke   = platform.request("O_sdram_cke")
+                    self.cs_n  = platform.request("O_sdram_cs_n")
+                    self.cas_n = platform.request("O_sdram_cas_n")
+                    self.ras_n = platform.request("O_sdram_ras_n")
+                    self.we_n  = platform.request("O_sdram_we_n")
+                    self.dm    = platform.request("O_sdram_dqm")
+                    self.a     = platform.request("O_sdram_addr")
+                    self.ba    = platform.request("O_sdram_ba")
+                    self.dq    = platform.request("IO_sdram_dq")
+            sdram_pads = SDRAMPads()
+
+            self.comb += sdram_pads.clk.eq(~ClockSignal("sys"))
+
+            sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
+            self.submodules.sdrphy = sdrphy_cls(sdram_pads, sys_clk_freq)
+            self.add_sdram("sdram",
+                phy                     = self.sdrphy,
+                module                  = M12L64322A(sys_clk_freq, sdram_rate),
+                origin                  = self.mem_map["main_ram"],
+                size                    = kwargs.get("max_sdram_size", 0x10000000),
+                l2_cache_size           = 0,
+                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
+                l2_cache_reverse        = True
+            )
+
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
@@ -68,11 +98,10 @@ class BaseSoC(SoCCore):
 # Flash --------------------------------------------------------------------------------------------
 
 def flash(offset, path):
-    from spiflash.serialflash import SerialFlashManager
+    # Create FTDI <--> SPI Flash proxy bitstream and load it.
     platform = tec0117.Platform()
-    flash = platform.request("spiflash", 0)
+    flash    = platform.request("spiflash", 0)
-    bus = platform.request("spiflash", 1)
+    bus      = platform.request("spiflash", 1)
-
     module = Module()
     module.comb += [
         flash.clk.eq(bus.clk),
@@ -80,26 +109,25 @@ def flash(offset, path):
         flash.mosi.eq(bus.mosi),
         bus.miso.eq(flash.miso),
     ]
-
     platform.build(module)
     prog = platform.create_programmer()
     prog.load_bitstream('build/impl/pnr/project.fs')
 
+    # Flash BIOS through proxy bitstream.
+    from spiflash.serialflash import SerialFlashManager
     dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
-    dev.TIMINGS['chip'] = (4, 60) # chip is too slow
+    dev.TIMINGS['chip'] = (4, 60) # Chip is too slow
     print("Erasing flash...")
     dev.erase(0, -1)
-
     with open(path, 'rb') as f:
         bios = f.read()
-
     print("Programming flash...")
     dev.write(offset, bios)
 
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
+    parser = argparse.ArgumentParser(description="LiteX SoC on TEC0117")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--load",              action="store_true", help="Load bitstream")
     parser.add_argument("--bios-flash-offset", default=0x00000,     help="BIOS offset in SPI Flash (0x00000 default)")
@@ -109,7 +137,7 @@ def main():
     soc_core_args(parser)
     args = parser.parse_args()
 
-    soc= BaseSoC(
+    soc = BaseSoC(
         bios_flash_offset = args.bios_flash_offset,
         sys_clk_freq      = int(float(args.sys_clk_freq)),
         **soc_core_argdict(args)
@@ -118,16 +146,11 @@ def main():
     builder.build(run=args.build)
 
     if args.flash:
-        flash(
+        flash(args.bios_flash_offset, os.path.join(builder.software_dir, "bios", "bios.bin"))
-            args.bios_flash_offset,
-            os.path.join(builder.software_dir, "bios", "bios.bin"))
 
     if args.load:
         prog = soc.platform.create_programmer()
-        prog.load_bitstream(
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"), args.flash)
-            os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"),
-            args.flash)
-
 
 if __name__ == "__main__":
     main()