Merge pull request #75 from jersey99/marblemini
Marblemini [https://github.com/berkeleylab/marble-mini/]
This commit is contained in:
enjoy-digital
GitHub
commit
4ffdcb5ea9
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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# TODO:
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# 1. TMDS lanes for the HDMI connector
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# 2. Populate more SFPs
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_io = [
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("clk20_vcxo", 0, Pins("D17"), IOStandard("LVCMOS33")),
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("vcxo_en", 0, Pins("E13"), IOStandard("LVCMOS33")), # Enable for the above clock
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("mgt_clk_0", 0,
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Subsignal("p", Pins("F6")),
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Subsignal("n", Pins("E6"))),
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("mgt_clk_1", 0,
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Subsignal("p", Pins("F10")),
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Subsignal("n", Pins("E10"))),
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("serial", 0,
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Subsignal("rts", Pins("W9")),
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Subsignal("rx", Pins("U7")),
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Subsignal("tx", Pins("Y9")),
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IOStandard("LVCMOS25")
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),
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("eth_clocks", 0,
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Subsignal("tx", Pins("J15"), Misc("SLEW=FAST")),
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Subsignal("rx", Pins("L19")),
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IOStandard("LVCMOS25")),
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("eth", 0, Subsignal("rx_ctl", Pins("H15"), Misc("IOB=TRUE")),
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Subsignal("rx_data", Pins("K13 H14 J14 K14"), Misc("IOB=TRUE")),
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Subsignal("tx_ctl", Pins("J16"), Misc("IOB=TRUE"), Misc("SLEW=FAST")),
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Subsignal("tx_data", Pins("G15 G16 G13 H13"), Misc("SLEW=FAST")),
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Subsignal("rst_n", Pins("M17")), IOStandard("LVCMOS25"),
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),
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("pmod", 0,
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Subsignal("pmod", Pins("C18 D22 E22 G21 D21 E21 F21 G22"), IOStandard("LVCMOS33"))),
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("pmod", 1,
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Subsignal("pmod", Pins("F13 C14 C15 D16 F14 F15 F16 E16"), IOStandard("LVCMOS33"))),
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# ("sfp", 0,
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# Subsignal("txp", Pins("AC10")),
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# Subsignal("txn", Pins("AD10")),
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# Subsignal("rxp", Pins("AC12")),
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# Subsignal("rxn", Pins("AD12")),
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# ),
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("ddram",
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0,
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Subsignal("a",
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Pins("L6 M5 P6 K6 M1 M3 N2 M6", "P1 P2 L4 N5 L3 R1 N3 E3"),
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IOStandard("SSTL135")),
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Subsignal("ba", Pins("L5 M2 N4"), IOStandard("SSTL135")),
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Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
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Subsignal("cas_n", Pins("J6"), IOStandard("SSTL135")),
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Subsignal("we_n", Pins("K3"), IOStandard("SSTL135")),
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# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")), # TODO: couldn't find chip select on Marble
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Subsignal("dm", Pins("G2 E2"), IOStandard("SSTL135")),
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Subsignal("dq",
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Pins("G3 J1 H4 H5 H2 K1 H3 J5", "G1 B1 F1 F3 C2 A1 D2 B2"),
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IOStandard("SSTL135")),
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Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL135")),
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Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL135")),
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Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL135")),
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Subsignal("cke", Pins("L1"), IOStandard("SSTL135")),
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Subsignal("odt", Pins("K4"), IOStandard("SSTL135")),
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Subsignal("reset_n", Pins("G4"), IOStandard("SSTL135"))
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),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [("LPC", {
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'CLK0_M2C_N': 'W20',
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'CLK0_M2C_P': 'W19',
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'CLK1_M2C_N': 'Y19',
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'CLK1_M2C_P': 'Y18',
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'LA00_N': 'V20',
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'LA00_P': 'U20',
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'LA01_N': 'V19',
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'LA01_P': 'V18',
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'LA02_N': 'R16',
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'LA02_P': 'P15',
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'LA03_N': 'N14',
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'LA03_P': 'N13',
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'LA04_N': 'W17',
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'LA04_P': 'V17',
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'LA05_N': 'R19',
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'LA05_P': 'P19',
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'LA06_N': 'AB18',
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'LA06_P': 'AA18',
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'LA07_N': 'AA21',
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'LA07_P': 'AA20',
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'LA08_N': 'P17',
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'LA08_P': 'N17',
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'LA09_N': 'T18',
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'LA09_P': 'R18',
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'LA10_N': 'AB20',
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'LA10_P': 'AA19',
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'LA11_N': 'R17',
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'LA11_P': 'P16',
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'LA12_N': 'U18',
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'LA12_P': 'U17',
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'LA13_N': 'W22',
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'LA13_P': 'W21',
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'LA14_N': 'AB22',
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'LA14_P': 'AB21',
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'LA15_N': 'Y22',
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'LA15_P': 'Y21',
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'LA16_N': 'R14',
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'LA16_P': 'P14',
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'LA17_N_CC': 'K19',
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'LA17_P_CC': 'K18',
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'LA18_N_CC': 'H19',
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'LA18_P_CC': 'J19',
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'LA19_N': 'J17',
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'LA19_P': 'K17',
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'LA20_N': 'L15',
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'LA20_P': 'L14',
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'LA21_N': 'N19',
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'LA21_P': 'N18',
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'LA22_N': 'L21',
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'LA22_P': 'M21',
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'LA23_N': 'M20',
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'LA23_P': 'N20',
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'LA24_N': 'H18',
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'LA24_P': 'H17',
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'LA25_N': 'L18',
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'LA25_P': 'M18',
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'LA26_N': 'G20',
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'LA26_P': 'H20',
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'LA27_N': 'M22',
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'LA27_P': 'N22',
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'LA28_N': 'M16',
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'LA28_P': 'M15',
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'LA29_N': 'K22',
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'LA29_P': 'K21',
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'LA30_N': 'K16',
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'LA30_P': 'L16',
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'LA31_N': 'H22',
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'LA31_P': 'J22',
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'LA32_N': 'G18',
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'LA32_P': 'G17',
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'LA33_N': 'J21',
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'LA33_P': 'J20'
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}), ("LPC-2", {
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'CLK0_M2C_N': 'W4',
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'CLK0_M2C_P': 'V4',
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'CLK1_M2C_N': 'T4',
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'CLK1_M2C_P': 'R4',
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'LA00_N': 'U5',
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'LA00_P': 'T5',
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'LA01_N': 'AA4',
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'LA01_P': 'Y4',
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'LA02_N': 'V3',
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'LA02_P': 'U3',
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'LA03_N': 'V2',
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'LA03_P': 'U2',
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'LA04_N': 'V5',
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'LA04_P': 'U6',
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'LA05_N': 'T6',
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'LA05_P': 'R6',
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'LA06_N': 'U1',
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'LA06_P': 'T1',
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'LA07_N': 'V8',
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'LA07_P': 'V9',
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'LA08_N': 'Y2',
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'LA08_P': 'W2',
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'LA09_N': 'AA3',
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'LA09_P': 'Y3',
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'LA10_N': 'Y1',
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'LA10_P': 'W1',
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'LA11_N': 'AA6',
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'LA11_P': 'Y6',
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'LA12_N': 'W5',
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'LA12_P': 'W6',
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'LA13_N': 'W7',
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'LA13_P': 'V7',
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'LA14_N': 'AB1',
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'LA14_P': 'AA1',
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'LA15_N': 'AB5',
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'LA15_P': 'AA5',
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'LA16_N': 'AB2',
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'LA16_P': 'AB3',
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'LA17_N': 'W12',
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'LA17_P': 'W11',
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'LA18_N': 'V14',
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'LA18_P': 'V13',
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'LA19_N': 'Y12',
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'LA19_P': 'Y11',
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'LA20_N': 'AA11',
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'LA20_P': 'AA10',
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'LA21_N': 'AA14',
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'LA21_P': 'Y13',
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'LA22_N': 'W16',
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'LA22_P': 'W15',
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'LA23_N': 'W10',
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'LA23_P': 'V10',
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'LA24_N': 'Y14',
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'LA24_P': 'W14',
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'LA25_N': 'AB12',
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'LA25_P': 'AB11',
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'LA26_N': 'AA16',
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'LA26_P': 'Y16',
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'LA27_N': 'AB10',
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'LA27_P': 'AA9',
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'LA28_N': 'T15',
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'LA28_P': 'T14',
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'LA29_N': 'U16',
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'LA29_P': 'T16',
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'LA30_N': 'V15',
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'LA30_P': 'U15',
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'LA31_N': 'AB13',
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'LA31_P': 'AA13',
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'LA32_N': 'AB15',
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'LA32_P': 'AA15',
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'LA33_N': 'AB17',
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'LA33_P': 'AB16'
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})]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(
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self, "xc7a100t-2fgg484", _io, _connectors, toolchain="vivado")
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# For now set to use the default VIVADO programmer, should be changed to xc3sprog
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self.toolchain.bitstream_commands = [
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"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
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]
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self.toolchain.additional_commands = [
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"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
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]
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self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
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self.add_platform_command("set_property CFGBVS VCCO [current_design]")
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self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
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def create_programmer(self):
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return OpenOCD("openocd_marblemini.cfg")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk20_vcxo", loose=True), 1e9 / 20e6)
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self.add_period_constraint(self.lookup_request("mgt_clk_0", loose=True), 1e9 / 125e6)
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@ -0,0 +1,41 @@
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# openocd config file for Marble Mini
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# https://github.com/BerkeleyLab/Marble-mini
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interface ftdi
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# This string needs programming into U21 EEPROM attached to U23 FT4232H
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# ftdi_device_desc "Marble Mini"
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# Pin assignment consistent with MPSSE Channel A, Table 3.14 for FT4232H-56Q
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# ADBUS0 (pin 12) USB_TCK
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# ADBUS1 (pin 13) USB_TDI
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# ADBUS2 (pin 14) USB_TDO
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# ADBUS3 (pin 15) USB_TMS
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# Additional pin, GPIOL0, set high
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# ADBUS4 (pin 17) EN_USB_JTAG
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# check logic of EN_USB_JTAG:
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# routed to U39-3 P0_2 for informational purposes
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# also to Q5, forces disable of Self_FPGA_* buffers
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# Default for FT4232H
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ftdi_vid_pid 0x0403 0x6011
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# Choose channel for FPGA JTAG, 0 == Channel A?
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ftdi_channel 0
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# Just TCK TDI TDO TMS, all other pins driven high.
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# Not sure what controls DBUS banks C, D, and maybe even B.
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ftdi_layout_init 0xfff8 0xfffb
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reset_config none
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# default speed
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adapter_khz 15000
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# Cribbed from openocd-code/tcl/board/kasli.cfg
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source [find cpld/xilinx-xc7.cfg]
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source [find cpld/jtagspi.cfg]
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# Following lines found in git head, but don't work with older openocd
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# version 0.10.0 available with apt-get in Debian Buster.
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# source [find fpga/xilinx-xadc.cfg]
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# source [find fpga/xilinx-dna.cfg]
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