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sitlinv_stlv7325: add video HDMI, enable compressed bitstream
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2 changed files with 31 additions and 0 deletions
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@ -8,11 +8,15 @@ from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform
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from litex.build.openocd import OpenOCD
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# This board is available here:
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# https://www.aliexpress.com/item/1005001275162791.html
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
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("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
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@ -294,6 +298,7 @@ class Platform(Xilinx7SeriesPlatform):
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self.add_platform_command("""
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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""")
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self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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@ -303,6 +308,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
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def do_finalize(self, fragment):
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Xilinx7SeriesPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
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self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)
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@ -39,11 +39,14 @@ class _CRG(LiteXModule):
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self.cd_sys = ClockDomain()
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self.cd_sys4x = ClockDomain()
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self.cd_idelay = ClockDomain()
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self.cd_hdmi = ClockDomain()
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self.cd_hdmi5x = ClockDomain()
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# # #
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# Clk/Rst.
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clk200 = platform.request("clk200")
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clk100 = platform.request("clk100")
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rst_n = platform.request("cpu_reset_n")
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# PLL.
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@ -55,6 +58,12 @@ class _CRG(LiteXModule):
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pll.create_clkout(self.cd_idelay, 200e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
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self.comb += pll2.reset.eq(~rst_n | self.rst)
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pll2.register_clkin(clk100, 100e6)
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pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)
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pll2.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
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self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -151,6 +160,16 @@ class BaseSoC(SoCCore):
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# Core
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self.add_sata(phy=self.sata_phy, mode="read+write")
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# HDMI Options -----------------------------------------------------------------------------
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if (with_video_colorbars or with_video_framebuffer or with_video_terminal):
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self.submodules.videophy = VideoS6HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.leds = LedChaser(
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@ -179,6 +198,12 @@ def main():
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sdopts = parser.target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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