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sitlinv_stlv7325: add video HDMI, enable compressed bitstream

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This commit is contained in:
Hans Baier 2023-04-07 07:29:47 +07:00
parent ae3d5d599b
commit 5067a2683f
2 changed files with 31 additions and 0 deletions
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6
litex_boards/platforms/sitlinv_stlv7325.py
View file

@ -8,11 +8,15 @@ from litex.build.generic_platform import *
from litex.build.xilinx import Xilinx7SeriesPlatform from litex.build.xilinx import Xilinx7SeriesPlatform
from litex.build.openocd import OpenOCD from litex.build.openocd import OpenOCD
# This board is available here:
# https://www.aliexpress.com/item/1005001275162791.html
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
_io = [ _io = [
# Clk / Rst # Clk / Rst
("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")), ("cpu_reset_n", 0, Pins("AC16"), IOStandard("LVCMOS15")),
("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")), ("clk100", 0, Pins("F17"), IOStandard("LVCMOS25")),
("clk200", 0, ("clk200", 0,
Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")), Subsignal("p", Pins("AB11"), IOStandard("DIFF_SSTL15")),
@ -294,6 +298,7 @@ class Platform(Xilinx7SeriesPlatform):
self.add_platform_command(""" self.add_platform_command("""
set_property CFGBVS VCCO [current_design] set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design] set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
""") """)
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
@ -303,6 +308,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
def do_finalize(self, fragment): def do_finalize(self, fragment):
Xilinx7SeriesPlatform.do_finalize(self, fragment) Xilinx7SeriesPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6) self.add_period_constraint(self.lookup_request("eth_clocks:tx", 0, loose=True), 1e9/125e6)

25
litex_boards/targets/sitlinv_stlv7325.py
View file

@ -39,11 +39,14 @@ class _CRG(LiteXModule):
self.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.cd_sys4x = ClockDomain() self.cd_sys4x = ClockDomain()
self.cd_idelay = ClockDomain() self.cd_idelay = ClockDomain()
self.cd_hdmi = ClockDomain()
self.cd_hdmi5x = ClockDomain()
# # # # # #
# Clk/Rst. # Clk/Rst.
clk200 = platform.request("clk200") clk200 = platform.request("clk200")
clk100 = platform.request("clk100")
rst_n = platform.request("cpu_reset_n") rst_n = platform.request("cpu_reset_n")
# PLL. # PLL.
@ -55,6 +58,12 @@ class _CRG(LiteXModule):
pll.create_clkout(self.cd_idelay, 200e6) pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.pll2 = pll2 = S7MMCM(speedgrade=-2)
self.comb += pll2.reset.eq(~rst_n | self.rst)
pll2.register_clkin(clk100, 100e6)
pll2.create_clkout(self.cd_hdmi, 25e6, margin=0)
pll2.create_clkout(self.cd_hdmi5x, 125e6, margin=0)
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
@ -151,6 +160,16 @@ class BaseSoC(SoCCore):
# Core # Core
self.add_sata(phy=self.sata_phy, mode="read+write") self.add_sata(phy=self.sata_phy, mode="read+write")
# HDMI Options -----------------------------------------------------------------------------
if (with_video_colorbars or with_video_framebuffer or with_video_terminal):
self.submodules.videophy = VideoS6HDMIPHY(platform.request("hdmi_out"), clock_domain="hdmi")
if with_video_colorbars:
self.add_video_colorbars(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", clock_domain="hdmi")
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser:
self.leds = LedChaser( self.leds = LedChaser(
@ -179,6 +198,12 @@ def main():
sdopts = parser.target_group.add_mutually_exclusive_group() sdopts = parser.target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.") sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.") sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
viopts = target_group.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (HDMI).")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args() args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip) assert not (args.with_etherbone and args.eth_dynamic_ip)