WIP sdram module option

litex_boards/community/platforms/de10nano.py

@@ -32,8 +32,6 @@ _io = [
         Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL"))  # Arduino_IO0
     ),
 
-    
-
     ("g_sensor", 0,
         Subsignal("int", Pins("A17")),
         Subsignal("sclk", Pins("C18")),
@@ -87,6 +85,26 @@ _io = [
     ),
 ]
 
+_mister_sdram_module_io = [
+    ("sdram_clock", 0, Pins("AD20"), IOStandard("3.3-V LVTTL")),
+    ("sdram", 0,
+        Subsignal("cke", Pins("AG10")),
+        Subsignal("a", Pins(
+            "Y11 AA26 AA13 AA11 W11 Y19 AB23 AC23 AC22 C12 AB26 AD17 D12")),
+        Subsignal("dq", Pins(
+            "E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")),
+        Subsignal("ba", Pins(
+            "Y17 AB25")),
+        Subsignal("dqmh", Pins("AF13")),
+        Subsignal("dqml", Pins("AG13")),
+        Subsignal("cas_n", Pins("AA18")),
+        Subsignal("cs_n", Pins("Y18")),
+        Subsignal("ras_n", Pins("W14")),
+        Subsignal("we_n", Pins("AA19")),
+        IOStandard("3.3-V LVTTL"), Misc("SLEWRATE=FAST")
+    ),
+]
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(AlteraPlatform):
@@ -94,7 +112,8 @@ class Platform(AlteraPlatform):
     default_clk_period = 1e9/50e6
 
     def __init__(self):
-        AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
+        # TODO uncancerify
+        AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io)
 
     def create_programmer(self):
         return USBBlaster()

litex_boards/community/targets/de10nano.py

@@ -11,8 +11,11 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 from litex_boards.platforms import de10nano
 
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 
+from litedram.modules import AS4C16M16
+from litedram.phy import GENSDRPHY
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -71,21 +74,52 @@ class BaseSoC(SoCCore):
         assert sys_clk_freq == int(50e6)
         platform = de10nano.Platform()
 
-        # SoCSDRAM ---------------------------------------------------------------------------------
+        # SoCCore ---------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform)
 
+
+# SDRAMSoC ------------------------------------------------------------------------------------------
+
+class SDRAMSoC(SoCSDRAM):
+    def __init__(self, sys_clk_freq=int(50e6), **kwargs):
+        assert sys_clk_freq == int(50e6)
+        platform = de10nano.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform)
+
+
+        # SDR SDRAM --------------------------------------------------------------------------------
+
+        self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+        sdram_module = AS4C16M16(self.clk_freq, "1:1")
+        self.register_sdram(self.sdrphy,
+            geom_settings   = sdram_module.geom_settings,
+            timing_settings = sdram_module.timing_settings)
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
+    parser.add_argument("--with-sdram", action="store_true",
+                        help="enable MiSTer SDRAM expansion board")
     builder_args(parser)
-    soc_core_args(parser)
+    #soc_core_args(parser) # TODO figure out how to get args for both
+                           # core and sdram SoCs without breaking shit
+    soc_sdram_args(parser)
     args = parser.parse_args()
+    soc = None
+    if args.with_sdram:
+        soc = SDRAMSoC(**soc_sdram_argdict(args)) 
+    else:
+        soc = BaseSoC(**soc_sdram_argdict(args)) 
 
-    soc = BaseSoC(**soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()