WIP sdram module option
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@ -32,8 +32,6 @@ _io = [
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Subsignal("rx", Pins("AG13"), IOStandard("3.3-V LVTTL")) # Arduino_IO0
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),
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("g_sensor", 0,
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Subsignal("int", Pins("A17")),
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Subsignal("sclk", Pins("C18")),
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@ -87,6 +85,26 @@ _io = [
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),
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]
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_mister_sdram_module_io = [
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("sdram_clock", 0, Pins("AD20"), IOStandard("3.3-V LVTTL")),
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("sdram", 0,
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Subsignal("cke", Pins("AG10")),
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Subsignal("a", Pins(
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"Y11 AA26 AA13 AA11 W11 Y19 AB23 AC23 AC22 C12 AB26 AD17 D12")),
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Subsignal("dq", Pins(
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"E8 V12 D11 W12 AH13 D8 AH14 AF7 AE24 AD23 AE6 AE23 AG14 AD5 AF4 AH3")),
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Subsignal("ba", Pins(
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"Y17 AB25")),
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Subsignal("dqmh", Pins("AF13")),
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Subsignal("dqml", Pins("AG13")),
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Subsignal("cas_n", Pins("AA18")),
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Subsignal("cs_n", Pins("Y18")),
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Subsignal("ras_n", Pins("W14")),
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Subsignal("we_n", Pins("AA19")),
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IOStandard("3.3-V LVTTL"), Misc("SLEWRATE=FAST")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(AlteraPlatform):
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@ -94,7 +112,8 @@ class Platform(AlteraPlatform):
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default_clk_period = 1e9/50e6
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def __init__(self):
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AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io)
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# TODO uncancerify
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AlteraPlatform.__init__(self, "5CSEBA6U23I7", _io+_mister_sdram_module_io)
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def create_programmer(self):
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return USBBlaster()
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@ -11,8 +11,11 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import de10nano
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import AS4C16M16
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from litedram.phy import GENSDRPHY
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# CRG ----------------------------------------------------------------------------------------------
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@ -71,21 +74,52 @@ class BaseSoC(SoCCore):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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# SoCCore ---------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDRAMSoC ------------------------------------------------------------------------------------------
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class SDRAMSoC(SoCSDRAM):
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def __init__(self, sys_clk_freq=int(50e6), **kwargs):
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assert sys_clk_freq == int(50e6)
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platform = de10nano.Platform()
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform)
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# SDR SDRAM --------------------------------------------------------------------------------
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = AS4C16M16(self.clk_freq, "1:1")
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self.register_sdram(self.sdrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano")
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parser.add_argument("--with-sdram", action="store_true",
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help="enable MiSTer SDRAM expansion board")
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builder_args(parser)
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soc_core_args(parser)
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#soc_core_args(parser) # TODO figure out how to get args for both
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# core and sdram SoCs without breaking shit
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = None
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if args.with_sdram:
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soc = SDRAMSoC(**soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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