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kx2: cleanup, fix copyright

This commit is contained in:
Florent Kermarrec 2020-01-13 17:22:33 +01:00
parent 3811b58f32
commit 50d550c911
2 changed files with 54 additions and 65 deletions
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8
litex_boards/community/platforms/kx2.py
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@ -1,4 +1,4 @@
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
# License: BSD # License: BSD
from litex.build.generic_platform import * from litex.build.generic_platform import *
@ -22,7 +22,7 @@ _io = [
("serial", 0, ("serial", 0,
Subsignal("tx", Pins("W11")), Subsignal("tx", Pins("W11")),
Subsignal("rx", Pins("AB16")), Subsignal("rx", Pins("AB16")),
IOStandard("LVCMOS15") # maybe LVCMOS15 or 33 IOStandard("LVCMOS15") # FIXME: LVCMOS15 or LVCMOS33?
), ),
("ddram", 0, ("ddram", 0,
@ -59,7 +59,6 @@ _io = [
Misc("SLEW=FAST"), Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH") Misc("VCCAUX_IO=HIGH")
), ),
] ]
@ -74,6 +73,3 @@ class Platform(XilinxPlatform):
def create_programmer(self): def create_programmer(self):
return VivadoProgrammer() return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

13
litex_boards/community/targets/kx2.py
View File

@ -1,8 +1,6 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk> # This file is Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
# License: BSD # License: BSD
import argparse import argparse
@ -42,14 +40,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs): def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kx2.Platform() platform = kx2.Platform()
# SoCSDRAM --------------------------------------------------------------------------------- # SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq) self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -66,14 +61,12 @@ class BaseSoC(SoCSDRAM):
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KX2") parser = argparse.ArgumentParser(description="LiteX SoC on KX2")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
# parser.add_argument(action="store_true")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(**soc_sdram_argdict(args))