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kx2: cleanup, fix copyright

This commit is contained in:
Florent Kermarrec 2020-01-13 17:22:33 +01:00
parent 3811b58f32
commit 50d550c911
2 changed files with 54 additions and 65 deletions
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10
litex_boards/community/platforms/kx2.py
View File

@ -1,4 +1,4 @@
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
# License: BSD
from litex.build.generic_platform import *
@ -22,7 +22,7 @@ _io = [
("serial", 0,
Subsignal("tx", Pins("W11")),
Subsignal("rx", Pins("AB16")),
IOStandard("LVCMOS15") # maybe LVCMOS15 or 33
IOStandard("LVCMOS15") # FIXME: LVCMOS15 or LVCMOS33?
),
("ddram", 0,
@ -59,7 +59,6 @@ _io = [
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
]
@ -67,13 +66,10 @@ _io = [
class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9 / 200e6
default_clk_period = 1e9/200e6
def __init__(self):
XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)

25
litex_boards/community/targets/kx2.py
View File

@ -1,8 +1,6 @@
#!/usr/bin/env python3
# This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
# This file is Copyright (c) 2020 Mark Standke <mstandke@cern.ch>
# License: BSD
import argparse
@ -33,7 +31,7 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("cpu_reset_n"))
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@ -42,14 +40,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(125e6), integrated_rom_size=0x8000, **kwargs):
def __init__(self, sys_clk_freq=int(125e6), **kwargs):
platform = kx2.Platform()
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
integrated_sram_size=0x8000,
**kwargs)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -57,15 +52,14 @@ class BaseSoC(SoCSDRAM):
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = H5TC4G63CFR(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings=sdram_module.geom_settings,
timing_settings=sdram_module.timing_settings)
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
# Build --------------------------------------------------------------------------------------------
@ -73,7 +67,6 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on KX2")
builder_args(parser)
soc_sdram_args(parser)
# parser.add_argument(action="store_true")
args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args))