mirror of
https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
terasic_deca: Review/Cleanup for consistency with other boards.
This commit is contained in:
Florent Kermarrec
parent
be4965ca78
commit
53a767c85c
2 changed files with 95 additions and 91 deletions
litex_boards
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@ -11,17 +11,14 @@ from litex.build.altera.programmer import USBBlaster
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# power button
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("pwr_but", 0, Pins("P9:9"), IOStandard("3.3-V LVTTL")),
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# system reset
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("sys_reset_n", 0, Pins("P9:10"), IOStandard("3.3-V LVTTL")),
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# Clk / Rst.
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("clk10", 0, Pins("M9"), IOStandard("2.5 V")),
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("clk50", 0, Pins("M8"), IOStandard("2.5 V")),
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("clk50", 1, Pins("P11"), IOStandard("3.3-V LVTTL")),
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("rst_n", 0, Pins("P9:10"), IOStandard("3.3-V LVTTL")),
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("power_btn", 0, Pins("P9:9"), IOStandard("3.3-V LVTTL")),
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# Clk
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("adc_clk_10", 0, Pins("M9"), IOStandard("2.5 V")),
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("clk1_50", 0, Pins("M8"), IOStandard("2.5 V")),
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("clk2_50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
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# Leds
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# Leds.
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("user_led", 0, Pins("C7"), IOStandard("1.2 V")),
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("user_led", 1, Pins("C8"), IOStandard("1.2 V")),
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("user_led", 2, Pins("A6"), IOStandard("1.2 V")),
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@ -31,22 +28,22 @@ _io = [
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("user_led", 6, Pins("B4"), IOStandard("1.2 V")),
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("user_led", 7, Pins("C5"), IOStandard("1.2 V")),
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# Button
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("key", 0, Pins("H21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("key", 1, Pins("H22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# Buttons.
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("user_btn", 0, Pins("H21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("user_btn", 1, Pins("H22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# Switches
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("sw", 0, Pins("J21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("sw", 1, Pins("J22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# Switches.
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("user_sw", 0, Pins("J21"), IOStandard("1.5 V SCHMITT TRIGGER")),
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("user_sw", 1, Pins("J22"), IOStandard("1.5 V SCHMITT TRIGGER")),
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# I2C: CapSense Buttons
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# CapSense Buttons (I2C).
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("cap_sense_i2c", 0,
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Subsignal("scl", Pins("AB2")),
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Subsignal("sda", Pins("AB3")),
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IOStandard("3.3-V LVTTL")
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),
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# board temperature sensor
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# Temperature sensor.
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("temp", 0,
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Subsignal("cs_n", Pins("PIN_AB4")),
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Subsignal("sc", Pins("PIN_AA1")),
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@ -54,7 +51,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# power monitor I2C
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# Power monitor (I2C).
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("pmonitor_i2c", 0,
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Subsignal("alert", Pins("Y4")),
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Subsignal("scl", Pins("Y3")),
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@ -62,7 +59,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# temperature and humidity sensor I2C
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# Temperature / Humidity sensor (I2C).
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("rh_temp_i2c", 0,
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Subsignal("drdy_n", Pins("AB9")),
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Subsignal("scl", Pins("Y10")),
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@ -70,7 +67,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# proximity / ambient light sensor
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# Proximity / Ambient light sensor (I2C).
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("proximity_i2c", 0,
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Subsignal("scl", Pins("Y8")),
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Subsignal("sda", Pins("AA8")),
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@ -78,7 +75,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# Accelerometer
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# Accelerometer.
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("gsensor", 0,
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Subsignal("sdi", Pins("C6")),
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Subsignal("sdo", Pins("D5")),
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@ -89,7 +86,7 @@ _io = [
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IOStandard("1.2 V")
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),
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# DDR3 SDRAM
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# DDR3 SDRAM.
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("ddram", 0,
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Subsignal("a", Pins(
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"E21 V20 V21 C20 Y21 J14 V18 U20",
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@ -138,7 +135,7 @@ _io = [
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Misc("CURRENT_STRENGTH_NEW=MAXIMUM CURRENT")
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),
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# Audio
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# Audio.
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("audio", 0,
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Subsignal("bclk", Pins("R14")),
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Subsignal("reset_n", Pins("M21")),
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@ -155,28 +152,29 @@ _io = [
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IOStandard("1.5 V")
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),
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# USB ULPI TUSB1210
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# USB ULPI (TUSB1210).
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("ulpi", 0,
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Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
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Subsignal("cs", Pins("J11"), IOStandard("1.8 V")),
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Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
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Subsignal("stp", Pins("J12"), IOStandard("1.8 V")),
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Subsignal("dir", Pins("J13"), IOStandard("1.8 V")),
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Subsignal("nxt", Pins("H12"), IOStandard("1.8 V")),
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Subsignal("reset_n", Pins("E16"), IOStandard("1.8 V")),
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Subsignal("fault_n", Pins("D8"), IOStandard("1.2 V")),
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Subsignal("cs", Pins("J11"), IOStandard("1.8 V")),
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Subsignal("clk", Pins("H11"), IOStandard("1.2 V")),
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Subsignal("stp", Pins("J12"), IOStandard("1.8 V")),
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Subsignal("dir", Pins("J13"), IOStandard("1.8 V")),
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Subsignal("nxt", Pins("H12"), IOStandard("1.8 V")),
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Subsignal("reset_n", Pins("E16"), IOStandard("1.8 V")),
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Subsignal("data", Pins("E12 E13 H13 E14 H14 D15 E15 F15"), IOStandard("1.8 V")),
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),
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# SDCard.
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("sdcard", 0,
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Subsignal("sel", Pins("P13"), IOStandard("3.3-V LVTTL")),
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Subsignal("fb_clk", Pins("R22")),
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Subsignal("clk", Pins("T20")),
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Subsignal("cmd", Pins("T21")),
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Subsignal("data", Pins("R18 T18 T19 R20")),
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Subsignal("sel", Pins("P13"), IOStandard("3.3-V LVTTL")),
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Subsignal("fb_clk", Pins("R22")),
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Subsignal("clk", Pins("T20")),
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Subsignal("cmd", Pins("T21")),
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Subsignal("data", Pins("R18 T18 T19 R20")),
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IOStandard("1.5 V")
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),
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# MII Ethernet
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# MII Ethernet.
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("eth_clocks", 0,
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Subsignal("tx", Pins("T5")),
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Subsignal("rx", Pins("T6")),
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@ -197,7 +195,7 @@ _io = [
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IOStandard("2.5 V"),
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),
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# HDMI
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# HDMI.
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("hdmi", 0,
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Subsignal("r", Pins("C18 D17 C17 C19 D14 B19 D13 A19")),
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Subsignal("g", Pins("C14 A17 B16 C15 A14 A15 A12 A16")),
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@ -210,12 +208,13 @@ _io = [
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Misc("FAST_OUTPUT_REGISTER ON"),
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IOStandard("1.8 V")
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),
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# HDMI_I2C
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# HDMI_I2C.
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("hdmi_i2c", 0,
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Subsignal("scl", Pins("C10")),
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Subsignal("sda", Pins("B15")),
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IOStandard("1.8 V")
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),
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# HDMI_I2S.
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("hdmi_i2s", 0,
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Subsignal("i2s", Pins("A9 A11 A8 B8")),
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Subsignal("mclk", Pins("A7")),
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@ -224,7 +223,7 @@ _io = [
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IOStandard("3.3-V LVTTL")
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),
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# MIPI
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# MIPI.
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("camera", 0,
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Subsignal("mclk", Pins("U3")),
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Subsignal("clkp", Pins("N5")),
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@ -236,7 +235,7 @@ _io = [
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Subsignal("core_en", Pins("V3")),
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IOStandard("2.5 V"),
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),
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# LP-MIPI
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# LP-MIPI.
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("camera", 1,
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Subsignal("mclk", Pins("U3"), IOStandard("2.5 V")),
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Subsignal("clkp", Pins("E11")),
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@ -251,20 +250,26 @@ _io = [
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IOStandard("2.5 V")
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),
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("gpio", 0, Pins("P8:3 P8:4 P8:5 P8:6 P8:7 P8:8 P8:9 P8:10",
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"P8:11 P8:12 P8:13 P8:14 P8:15 P8:16 P8:17 P8:18",
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"P8:19 P8:20 P8:21 P8:22 P8:23 P8:24 P8:25 P8:26",
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"P8:27 P8:28 P8:29 P8:30 P8:31 P8:32 P8:33 P8:34",
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"P8:35 P8:36 P8:37 P8:38 P8:39 P8:40 P8:41 P8:42",
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"P8:43 P8:44 P8:45 P8:46"),
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IOStandard("3.3-V LVTTL")
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),
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("gpio", 1, Pins("P9:11 P9:12 P9:13 P9:14 P9:15 P9:16 P9:17 P9:18",
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"P9:19 P9:20 P9:21 P9:22 P9:23 P9:24 P9:25 P9:26",
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"P9:27 P9:28 P9:29 P9:30 P9:31 P9:41 P9:42"),
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IOStandard("3.3-V LVTTL")
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# GPIO 0.
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("gpio", 0, Pins(
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"P8:3 P8:4 P8:5 P8:6 P8:7 P8:8 P8:9 P8:10",
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"P8:11 P8:12 P8:13 P8:14 P8:15 P8:16 P8:17 P8:18",
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"P8:19 P8:20 P8:21 P8:22 P8:23 P8:24 P8:25 P8:26",
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"P8:27 P8:28 P8:29 P8:30 P8:31 P8:32 P8:33 P8:34",
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"P8:35 P8:36 P8:37 P8:38 P8:39 P8:40 P8:41 P8:42",
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"P8:43 P8:44 P8:45 P8:46"),
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IOStandard("3.3-V LVTTL")
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),
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# GPIO 1.
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("gpio", 1, Pins(
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"P9:11 P9:12 P9:13 P9:14 P9:15 P9:16 P9:17 P9:18",
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"P9:19 P9:20 P9:21 P9:22 P9:23 P9:24 P9:25 P9:26",
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"P9:27 P9:28 P9:29 P9:30 P9:31 P9:41 P9:42"),
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IOStandard("3.3-V LVTTL")
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),
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# GPIO Serial.
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("gpio_serial", 0,
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Subsignal("tx", Pins("P8:3")),
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Subsignal("rx", Pins("P8:4")),
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@ -289,7 +294,7 @@ class Platform(AlteraPlatform):
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def __init__(self):
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AlteraPlatform.__init__(self, "10M50DAF484C6GES", _io, _connectors)
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# disable config pin so bank8 can use 1.2V
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# Disable config pin so bank8 can use 1.2V.
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self.add_platform_command("set_global_assignment -name AUTO_RESTART_CONFIGURATION ON")
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self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
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self.add_platform_command("set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF")
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@ -300,4 +305,4 @@ class Platform(AlteraPlatform):
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def do_finalize(self, fragment):
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AlteraPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk1_50", loose=True), 1e9/50e6)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -10,19 +10,19 @@ import os
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import argparse
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from migen import *
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from litex_boards.platforms import deca
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from litex_boards.platforms import deca
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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from litex.soc.cores.clock import Max10PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoDVIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.cores.bitbang import I2CMaster
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_hdmi = ClockDomain()
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@ -30,25 +30,24 @@ class _CRG(Module):
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# # #
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# PLL
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ulpi = platform.request("ulpi", 0)
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clk1_50 = platform.request("clk1_50")
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# Clk / Rst.
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clk50 = platform.request("clk50")
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# PLL
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self.submodules.pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk1_50, 50e6)
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pll.register_clkin(clk50, 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_hdmi, 40e6)
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self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
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self.comb += [
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pll.reset.eq(self.rst),
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ulpi.cs.eq(1) # enable ULPI chip, which enables the ULPI clock
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]
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pll.register_clkin(ulpi.clk, 60e6)
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# the working example from the DECA kit uses -120 degrees for the USB core's
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# and it works with the LUNA core too
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pll.create_clkout(self.cd_usb, 60e6, phase=-120)
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# USB PLL.
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if with_usb_pll:
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ulpi = platform.request("ulpi")
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self.comb += ulpi.cs.eq(1) # Enable ULPI chip to enable the ULPI clock.
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self.submodules.usb_pll = pll = Max10PLL(speedgrade="-6")
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(ulpi.clk, 60e6)
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pll.create_clkout(self.cd_usb, 60e6, phase=-120) # -120° from DECA's example (also validated with LUNA).
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -56,36 +55,36 @@ class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(50e6), with_video_terminal=False, **kwargs):
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self.platform = platform = deca.Platform()
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq)
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Defaults to UART over JTAG because no hardware uart is on the board
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# Defaults to JTAG-UART since no hardware UART.
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "jtag_atlantic"
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Terasic DECA",
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ident_version = True,
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ident = "LiteX SoC on Terasic DECA",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = self.crg = _CRG(platform, sys_clk_freq, with_usb_pll=False)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal:
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self.submodules.videophy = VideoDVIPHY(platform.request("hdmi"), clock_domain="hdmi")
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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# Leds -------------------------------------------------------------------------------------
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on DECA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--debug", action="store_true", help="generate cpu debug interface")
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parser.add_argument("--debug", action="store_true", help="generate cpu debug interface") # FIXME: Remove or add argument in LiteX directly.
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parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
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parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
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parser.add_argument("--integrated-ram-size", default=0x4000, help="Use FPGA block RAM as main RAM. Interim measure until we have DDR3 support.")
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@ -97,8 +96,8 @@ def main():
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_video_terminal = args.with_video_terminal,
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integrated_main_ram_size = args.integrated_ram_size,
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# use compressed instructions to save ROM
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cpu_variant = "imac+debug" if args.debug else "imac",
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# Use compressed instructions to save ROM
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cpu_variant = "imac+debug" if args.debug else "imac", # FIXME: Remove or add argument in LiteX directly.
|
||||
**soc_core_argdict(args)
|
||||
)
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
|
|
|
|||
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Reference in a new issue