platforms/crosslink_nx_evn: allow use of UARTBone
This goes along a small resistor jumper modification and firmware flashing like it is for the ECP5 board. A warning message is added as the default serial might be affected (--serial serial by default). The FTDI modification software used for the ECP5 seems to be requried and matching. This can be tested this way: targets/lattice_crosslink_nx_evn.py --csr-csv=csr.csv --toolchain=oxide --programmer=openocd --uart-name crossover+uartbone --build --load litex_server --uart --uart-port /dev/ttyUSB1 litex_cli --regs
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@ -259,6 +259,16 @@ class Platform(LatticeNexusPlatform):
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assert device in ["LIFCL-40-9BG400C", "LIFCL-40-8BG400CES"]
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LatticeNexusPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain, **kwargs)
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def request(self, *args, **kwargs):
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import time
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if "serial" in args:
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msg = "FT2232H will be used as serial, make sure that:\n"
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msg += " -the hardware has been modified: R18 and R19 should be removed, two 0 Ω resistors shoud be populated on R15 (and not R16) and R17.\n"
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msg += " -the chip is configured as UART with virtual COM on port B (With FTProg or https://github.com/trabucayre/fixFT2232_ecp5evn)."
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print(msg)
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time.sleep(2)
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return LatticeNexusPlatform.request(self, *args, **kwargs)
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def create_programmer(self, mode = "direct", prog="radiant"):
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assert mode in ["direct","flash"]
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assert prog in ["radiant","ecpprog"]
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@ -92,6 +92,12 @@ class BaseSoC(SoCCore):
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pads = Cat(*[platform.request("user_led", i) for i in range(14)]),
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sys_clk_freq = sys_clk_freq)
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# UARTBone ---------------------------------------------------------------------------------
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debug_uart = False
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if debug_uart:
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self.add_uartbone()
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# Build --------------------------------------------------------------------------------------------
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def main():
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