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https://github.com/litex-hub/litex-boards.git
synced 2025-01-03 03:43:36 -05:00
xilinx_alveo_u280: Fix DDR4 (tested with 8 modules on C0 and C1).
This commit is contained in:
Sergiu Mosanu
Florent Kermarrec
parent
d830ef8393
commit
5519c931f8
2 changed files with 37 additions and 34 deletions
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@ -13,14 +13,13 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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_io = [
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# Clk / Rst
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("sysclk", 0,
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Subsignal("n", Pins("BJ44"), IOStandard("LVDS")),
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Subsignal("p", Pins("BJ43"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ44"), IOStandard("DIFF_SSTL12")),
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Subsignal("p", Pins("BJ43"), IOStandard("DIFF_SSTL12")),
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),
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("sysclk", 1,
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Subsignal("n", Pins("BJ6"), IOStandard("LVDS")),
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Subsignal("p", Pins("BH6"), IOStandard("LVDS")),
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Subsignal("n", Pins("BJ6"), IOStandard("DIFF_SSTL12")),
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Subsignal("p", Pins("BH6"), IOStandard("DIFF_SSTL12")),
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),
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("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
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# Leds
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@ -46,16 +45,18 @@ _io = [
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("ddram", 0,
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Subsignal("a", Pins(
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"BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43",
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"BK43 BM42 BG45 BD41 BL42 BE44"),
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"BK43 BM42 BG45 BD41 BL42 BE44"), # we_n=BE43 cas_n=BL46 ras_n=BH44
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IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31",
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"BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32",
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@ -65,40 +66,42 @@ _io = [
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"BE50 BE49 BE51 BD51 BF52 BF51 BG50 BF50",
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"BH50 BJ51 BH51 BH49 BK50 BK51 BJ49 BJ48",
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"BN44 BN45 BM44 BM45 BP43 BP44 BN47 BP47"),
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# ECC excluded 8 pins
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# "BG54 BG53 BE53 BE54 BH52 BG52 BK54 BK53"
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins(
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"BN30 BM29 BK30 BG30 BM35 BN35 BK35 BJ32",
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"BM50 BP49 BF48 BG49 BJ47 BK49 BP46 BP42"), #"BJ54 BJ53"
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IOStandard("DIFF_POD12"),
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IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins(
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"BN29 BM28 BJ29 BG29 BL35 BM34 BK34 BH32",
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"BM49 BP48 BF47 BG48 BH47 BK48 BN46 BN42"), #"BH54 BJ52"
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IOStandard("DIFF_POD12"),
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IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")),
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Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
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Misc("SLEW=FAST")
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),
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("ddram", 1,
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Subsignal("a", Pins(
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"BF7 BK1 BF6 BF5 BE3 BE6 BE5 BG7",
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"BJ1 BG2 BJ8 BE4 BL2 BK5"), # BK8 BJ4 BF8
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"BJ1 BG2 BJ8 BE4 BL2 BK5"), # we_n=BK8 cas_n=BJ4 ras_n=BF8
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IOStandard("SSTL12_DCI")),
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Subsignal("we_n", Pins("BK8"), IOStandard("SSTL12_DCI")), # A14
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Subsignal("cas_n", Pins("BJ4"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("ras_n", Pins("BF8"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("act_n", Pins("BG3"), IOStandard("SSTL12_DCI")),
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Subsignal("ba", Pins("BG8 BK4"), IOStandard("SSTL12_DCI")),
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Subsignal("bg", Pins("BF3 BF2"), IOStandard("SSTL12_DCI")),
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Subsignal("cas_n", Pins("BJ4"), IOStandard("SSTL12_DCI")), # A15
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Subsignal("cke", Pins("BE1"), IOStandard("SSTL12_DCI")),
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Subsignal("clk_n", Pins("BJ2"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("clk_p", Pins("BJ3"), IOStandard("DIFF_SSTL12_DCI")),
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Subsignal("cs_n", Pins("BL3"), IOStandard("SSTL12_DCI")),
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Subsignal("cs_n", Pins("BL3"), IOStandard("SSTL12_DCI")),
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Subsignal("dq", Pins(
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"A11 A10 A9 A8 B12 B10 C12 B11",
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"E11 D11 E12 F11 F10 E9 F9 G11",
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@ -108,25 +111,25 @@ _io = [
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"BJ9 BK9 BK10 BL10 BM9 BN9 BN10 BM10",
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"BM15 BM14 BL15 BM13 BN12 BM12 BP13 BP14",
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"BJ13 BJ12 BH15 BH14 BK14 BK15 BL12 BL13"),
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# ECC excluded 8 pins
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# "BE9 BE10 BF10 BE11 BG13 BG12 BG9 BG10"
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IOStandard("POD12_DCI"),
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_n", Pins(
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"A13 D9 G15 D14 BM7 BM8 BN14 BK13",
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"BF11 C9 G10 K13 D12 BP6 BP8 BP11"), # "BK11 BH9"
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IOStandard("DIFF_POD12"),
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"A13 C9 D9 G10 G15 K13 D14 D12",
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"BM7 BP6 BM8 BP8 BN14 BP11 BK13 BK11"), #"BF11 BH9"
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IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("dqs_p", Pins(
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"B13 C10 D10 H10 H15 K14 D15 E13",
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"BL7 BP7 BL8 BP9 BN15 BP12 BJ14 BJ11"), #"BH54 BJ52"
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IOStandard("DIFF_POD12"),
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"BL7 BP7 BL8 BP9 BN15 BP12 BJ14 BJ11"), #"BF12 BH10"
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IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
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Misc("PRE_EMPHASIS=RDRV_240"),
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Misc("EQUALIZATION=EQ_LEVEL2")),
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Subsignal("odt", Pins("BH2"), IOStandard("SSTL12_DCI")),
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Subsignal("ras_n", Pins("BF8"), IOStandard("SSTL12_DCI")), # A16
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Subsignal("reset_n", Pins("BH12"), IOStandard("LVCMOS12")),
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Subsignal("we_n", Pins("BK8"), IOStandard("SSTL12_DCI")), # A14
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Misc("SLEW=FAST")
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),
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]
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@ -166,12 +169,12 @@ class Platform(XilinxPlatform):
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self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 70]")
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# Other suggested configurations
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self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")
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self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]")
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self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]")
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# self.add_platform_command("set_property CONFIG_VOLTAGE 1.8 [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]")
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# self.add_platform_command("set_property CONFIG_MODE SPIx4 [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]")
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# self.add_platform_command("set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]")
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@ -41,7 +41,7 @@ class _CRG(Module):
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_idelay, 500e6)
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pll.create_clkout(self.cd_idelay, 600e6, with_reset=False)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.specials += [
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@ -57,7 +57,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(125e6), ddram_channel=0, with_pcie=False, **kwargs):
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def __init__(self, sys_clk_freq=int(150e6), ddram_channel=0, with_pcie=False, **kwargs):
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platform = alveo_u280.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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@ -104,7 +104,7 @@ def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U280")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)")
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parser.add_argument("--sys-clk-freq", default=150e6, help="System clock frequency (default: 150MHz)")
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parser.add_argument("--ddram-channel",default="0", help="DDRAM channel (default: 0)")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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