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xilinx_alveo_u2x0: Improve indentation on DRAMs.

This commit is contained in:
Florent Kermarrec 2023-01-16 09:34:59 +01:00
parent be77f82720
commit 55fcb4cd47
2 changed files with 41 additions and 41 deletions
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56
litex_boards/platforms/xilinx_alveo_u250.py
View File

@ -69,13 +69,13 @@ _io = [
"BA37 BB37 AR35 BA39 BB40 AN36"),
IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("BB39"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BC37 BC39"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AT35 AT34"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BC37 BC39"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("AP36"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BC38"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BC38"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("AW38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("AV38"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("AR33"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"AW28 AW29 BA28 BA27 BB29 BA29 BC27 BB27",
"BE28 BF28 BE30 BD30 BF27 BE27 BF30 BF29",
@ -100,10 +100,10 @@ _io = [
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AP34"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AR36"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AU31"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("AP35"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST")
),
("ddram", 1,
@ -112,13 +112,13 @@ _io = [
"AY25 BA23 AM26 BA25 BB22 AL24"),
IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AW25"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AU24 AP26"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BC22 AW26"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AU24 AP26"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BC22 AW26"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("AM25"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BB25"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BB25"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("AU25"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("AT25"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("AV23"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("AV23"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"BD9 BD7 BC7 BD8 BD10 BE10 BE7 BF7",
"AU13 AV13 AW13 AW14 AU14 AY11 AV14 BA11",
@ -143,10 +143,10 @@ _io = [
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("AW23"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AN23"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AW23"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AN23"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AR17"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("AL25"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST")
),
("ddram", 2,
@ -155,13 +155,13 @@ _io = [
"A32 D31 A34 E31 M30 F33"),
IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("B31"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("D33 B36"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("C31 J30"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("D33 B36"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("C31 J30"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("G32"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("G30"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("G30"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("B34"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("C34"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("B35"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("B35"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"R25 P25 M25 L25 P26 R26 N27 N28",
"J28 H29 H28 G29 K25 L27 K26 K27",
@ -186,10 +186,10 @@ _io = [
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("E33"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("K30"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("E33"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("K30"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("D36"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("A35"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST")
),
("ddram", 3,
@ -198,13 +198,13 @@ _io = [
"F13 A13 D14 C13 B13 K16"),
IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("H13"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("J15 H14"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("D13 J13"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("J15 H14"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("D13 J13"), IOStandard("SSTL12_DCI")),
Subsignal("cas_n", Pins("E15"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("K13"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("K13"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("L13"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("L14"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("B16"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("B16"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"P24 N24 T24 R23 N23 P21 P23 R21",
"J24 J23 H24 G24 L24 L23 K22 K21",
@ -229,10 +229,10 @@ _io = [
IOStandard("DIFF_POD12"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("C16"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("C16"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("F15"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("D21"), IOStandard("LVCMOS12")),
Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("D15"), IOStandard("SSTL12_DCI")),
Misc("SLEW=FAST")
),

26
litex_boards/platforms/xilinx_alveo_u280.py
View File

@ -46,16 +46,16 @@ _io = [
"BF46 BG43 BK45 BF42 BL45 BF43 BG42 BL43",
"BK43 BM42 BG45 BD41 BL42 BE44"), # we_n=BE43 cas_n=BL46 ras_n=BH44
IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
Subsignal("we_n", Pins("BE43"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cas_n", Pins("BL46"), IOStandard("SSTL12_DCI")), # A15
Subsignal("ras_n", Pins("BH44"), IOStandard("SSTL12_DCI")), # A16
Subsignal("act_n", Pins("BH41"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("BH45 BM47"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF41 BE41"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BH42"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("BJ46"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("BH46"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("BK46"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"BN32 BP32 BL30 BM30 BP29 BP28 BP31 BN31",
"BJ31 BH31 BF32 BF33 BH29 BH30 BF31 BG32",
@ -82,25 +82,25 @@ _io = [
IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("BG44"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("BG33"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST")
),
("ddram", 1,
("ddram", 1,
Subsignal("a", Pins(
"BF7 BK1 BF6 BF5 BE3 BE6 BE5 BG7",
"BJ1 BG2 BJ8 BE4 BL2 BK5"), # we_n=BK8 cas_n=BJ4 ras_n=BF8
IOStandard("SSTL12_DCI")),
Subsignal("we_n", Pins("BK8"), IOStandard("SSTL12_DCI")), # A14
Subsignal("we_n", Pins("BK8"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cas_n", Pins("BJ4"), IOStandard("SSTL12_DCI")), # A15
Subsignal("ras_n", Pins("BF8"), IOStandard("SSTL12_DCI")), # A16
Subsignal("act_n", Pins("BG3"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("BG8 BK4"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF3 BF2"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BE1"), IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("BG8 BK4"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("BF3 BF2"), IOStandard("SSTL12_DCI")),
Subsignal("cke", Pins("BE1"), IOStandard("SSTL12_DCI")),
Subsignal("clk_n", Pins("BJ2"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_p", Pins("BJ3"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cs_n", Pins("BL3"), IOStandard("SSTL12_DCI")),
Subsignal("cs_n", Pins("BL3"), IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"A11 A10 A9 A8 B12 B10 C12 B11",
"E11 D11 E12 F11 F10 E9 F9 G11",
@ -127,7 +127,7 @@ _io = [
IOStandard("DIFF_POD12"), # DIFF_POD12_DCI
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("odt", Pins("BH2"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("BH2"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("BH12"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST")
),