Merge pull request #178 from yetifrisstlama/vc707_clk

fix vc707 default_clk_period
2021-02-23 12:17:45 +01:00 · 2021-02-23 12:17:45 +01:00 · 5b28c619d5
parent a90c0bc8f9 09c3bd616b
commit 5b28c619d5
1 changed files with 1 additions and 1 deletions
--- a/litex_boards/platforms/vc707.py
+++ b/litex_boards/platforms/vc707.py
@ -629,7 +629,7 @@ _connectors = [

 class Platform(XilinxPlatform):
    default_clk_name   = "clk156"
-    default_clk_period = 1e9/156.5e6
+    default_clk_period = 1e9/156.25e6

    def __init__(self):
        XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")