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Merge pull request #178 from yetifrisstlama/vc707_clk 

fix vc707 default_clk_period
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enjoy-digital 2021-02-23 12:17:45 +01:00 committed by GitHub
parent a90c0bc8f9 09c3bd616b
commit 5b28c619d5
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litex_boards/platforms/vc707.py
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@ -629,7 +629,7 @@ _connectors = [
class Platform(XilinxPlatform): class Platform(XilinxPlatform):
default_clk_name = "clk156" default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6 default_clk_period = 1e9/156.25e6
def __init__(self): def __init__(self):
XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado") XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")