targets/alinx_axu2cga: adding PS software support (inspired by xilinx_kv260)
This commit is contained in:
Gwenhael Goavec-Merou
parent
50654f1b7b
commit
5eca41ac73
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@ -6,53 +6,110 @@
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# Copyright (c) 2022 Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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# SPDX-License-Identifier: BSD-2-Clause
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# Build/Use:
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# The current support is sufficient to run LiteX BIOS on Cortex-A53 core #0:
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# ./alinx_axu2cga.py --build --load
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# LiteX BIOS can then be executed on hardware using JTAG with the following xsct script from:
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# https://github.com/trabucayre/litex-template/
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# make -f Makefile.axu2cga load will build everything and run xsct in the end.
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#
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# Relies on https://github.com/lucaceresoli/zynqmp-pmufw-builder to create a generic PMU firmware;
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# first build will take a while because it includes a cross-toolchain.
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import axu2cga
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from litex_boards.platforms import alinx_axu2cga
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.build.tools import write_to_file
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq, use_psu_clk=False):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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# Clk
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clk25 = platform.request("clk25")
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if use_psu_clk:
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self.comb += [
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ClockSignal("sys").eq(ClockSignal("ps")),
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ResetSignal("sys").eq(ResetSignal("ps") | self.rst),
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]
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else:
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# Clk
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clk25 = platform.request("clk25")
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# PLL
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self.submodules.pll = pll = USMMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# PLL
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self.submodules.pll = pll = USMMCM(speedgrade=-1)
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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# Ignore sys_clk to pll.clkin path created by SoC's rst.
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
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platform = axu2cga.Platform()
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platform = alinx_axu2cga.Platform()
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if kwargs.get("cpu_type", None) == "zynqmp":
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kwargs['integrated_sram_size'] = 0
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kwargs['with_uart'] = False
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self.mem_map = {
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'csr': 0x8000_0000, # Zynq GP0 default
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}
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Alinx AXU2CGA",
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**kwargs)
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# ZynqMP Integration ---------------------------------------------------------------------
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if kwargs.get("cpu_type", None) == "zynqmp":
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self.cpu.config.update(platform.psu_config)
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# Connect AXI HPM0 LPD to the SoC
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wb_lpd = wishbone.Interface()
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self.submodules += axi.AXI2Wishbone(
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axi = self.cpu.add_axi_gp_master(2, 32),
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wishbone = wb_lpd,
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base_address = self.mem_map['csr'])
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self.add_wb_master(wb_lpd)
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self.bus.add_region("sram", SoCRegion(
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origin=self.cpu.mem_map["sram"],
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size=1 * 1024 * 1024 * 1024) # DDR
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)
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self.bus.add_region("rom", SoCRegion(
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origin=self.cpu.mem_map["rom"],
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size=512 * 1024 * 1024 // 8,
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linker=True)
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)
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self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127
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use_psu_clk = True
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else:
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use_psu_clk = False
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.submodules.crg = _CRG(platform, sys_clk_freq, use_psu_clk)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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@ -60,6 +117,64 @@ class BaseSoC(SoCCore):
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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def finalize(self, *args, **kwargs):
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super(BaseSoC, self).finalize(*args, **kwargs)
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if self.cpu_type != "zynqmp":
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return
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libxil_path = os.path.join(self.builder.software_dir, 'libxil')
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os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
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lib = os.path.join(libxil_path, 'embeddedsw')
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if not os.path.exists(lib):
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os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
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os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
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for header in [
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'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
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'lib/bsp/standalone/src/common/xil_types.h',
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'lib/bsp/standalone/src/common/xil_assert.h',
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'lib/bsp/standalone/src/common/xil_io.h',
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'lib/bsp/standalone/src/common/xil_printf.h',
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'lib/bsp/standalone/src/common/xstatus.h',
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'lib/bsp/standalone/src/common/xdebug.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xpseudo_asm.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xreg_cortexa53.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_errata.h',
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'lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h',
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'lib/bsp/standalone/src/arm/common/xil_exception.h',
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'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
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]:
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shutil.copy(os.path.join(lib, header), self.builder.include_dir)
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write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'), """
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#ifndef BSPCONFIG_H
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#define BSPCONFIG_H
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#define EL3 1
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#define EL1_NONSECURE 0
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#endif
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""")
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write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
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#ifndef XPARAMETERS_H
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#define XPARAMETERS_H
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#include "xparameters_ps.h"
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#define STDIN_BASEADDRESS 0xFF010000
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#define STDOUT_BASEADDRESS 0xFF010000
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#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
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#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
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#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
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#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
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#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99999005
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#endif
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''')
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# Build --------------------------------------------------------------------------------------------
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def main():
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@ -71,18 +186,24 @@ def main():
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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parser.set_defaults(cpu_type="zynqmp")
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sys_clk_freq=int(float(args.sys_clk_freq)),
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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if args.cpu_type == "zynqmp":
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soc.builder = builder
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builder.add_software_package('libxil')
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builder.add_software_library('libxil')
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builder.build(**vivado_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer(args.cable)
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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