Add initial Decklink Quad HDMI Recorder support (with documented PCIe/HDMI In).
LitePCIe Gen3 X4 enumerating correctly.
This commit is contained in:
Florent Kermarrec
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8ec1435e65
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst (SI5338A).
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# TODO (We'll use the 100MHz PCIe Clock for now).
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# SPIFlash (MX25L25645GSXDI).
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# TODO (Probably similar to KCU105).
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# PCIe
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("pcie_x1", 0,
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#Subsignal("rst_n", Pins(""), IOStandard("")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2")),
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Subsignal("rx_n", Pins("AB1")),
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Subsignal("tx_p", Pins("AC4")),
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Subsignal("tx_n", Pins("AC3"))
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),
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("pcie_x2", 0,
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#Subsignal("rst_n", Pins(""), IOStandard("")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2")),
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Subsignal("rx_n", Pins("AB1 AD1")),
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Subsignal("tx_p", Pins("AC4 AE4")),
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Subsignal("tx_n", Pins("AC3 AE3"))
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),
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("pcie_x4", 0,
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#Subsignal("rst_n", Pins(""), IOStandard("")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
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Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
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Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")),
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Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5"))
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),
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("pcie_x8", 0,
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#Subsignal("rst_n", Pins(""), IOStandard("")),
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Subsignal("clk_p", Pins("AB6")),
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Subsignal("clk_n", Pins("AB5")),
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Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
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Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
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Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
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Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
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),
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# HDMI (through PI3HDX1204)
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("hdmi_in", 0, # PCIe Edge Side.
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#Subsignal("clk_p", Pins(""), IOStandard("")),
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#Subsignal("clk_n", Pins(""), IOStandard("")),
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Subsignal("data0_p", Pins("Y2")),
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Subsignal("data0_n", Pins("Y1")),
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Subsignal("data1_p", Pins("V2")),
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Subsignal("data1_n", Pins("V1")),
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Subsignal("data2_p", Pins("T2")),
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Subsignal("data2_n", Pins("T1")),
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),
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("hdmi_in", 1,
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#Subsignal("clk_p", Pins(""), IOStandard("")),
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#Subsignal("clk_n", Pins(""), IOStandard("")),
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Subsignal("data0_p", Pins("P2")),
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Subsignal("data0_n", Pins("P1")),
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Subsignal("data1_p", Pins("M2")),
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Subsignal("data1_n", Pins("M1")),
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Subsignal("data2_p", Pins("K2")),
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Subsignal("data2_n", Pins("K1")),
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),
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("hdmi_in", 2,
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#Subsignal("clk_p", Pins(""), IOStandard("")),
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#Subsignal("clk_n", Pins(""), IOStandard("")),
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Subsignal("data0_p", Pins("H2")),
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Subsignal("data0_n", Pins("H1")),
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Subsignal("data1_p", Pins("F2")),
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Subsignal("data1_n", Pins("F1")),
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Subsignal("data2_p", Pins("E4")),
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Subsignal("data2_n", Pins("E3")),
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),
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("hdmi_in", 3,
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#Subsignal("clk_p", Pins(""), IOStandard("")),
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#Subsignal("clk_n", Pins(""), IOStandard("")),
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Subsignal("data0_p", Pins("D2")),
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Subsignal("data0_n", Pins("D1")),
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Subsignal("data1_p", Pins("B2")),
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Subsignal("data1_n", Pins("B1")),
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Subsignal("data2_p", Pins("B4")),
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Subsignal("data2_n", Pins("B3")),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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def __init__(self):
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XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, toolchain="vivado")
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def create_programmer(self):
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return VivadoProgrammer()
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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@ -0,0 +1,93 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import quad_hdmi_recorder
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litepcie.phy.uspciephy import USPCIEPHY
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from litepcie.software import generate_litepcie_software
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(ResetSignal("pcie"))
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pll.register_clkin(ClockSignal("pcie"), 250e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, **kwargs):
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platform = quad_hdmi_recorder.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["uart_name"] = "crossover"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Blackmagic Decklink Quad HDMI Recorder",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# PCIe -------------------------------------------------------------------------------------
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if with_pcie:
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self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
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speed = "gen3",
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data_width = 128,
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bar0_size = 0x20000)
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self.add_pcie(phy=self.pcie_phy, ndmas=1)
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# False Paths (FIXME: Improve integration).
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platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks main_clkout_1] -to [get_clocks pcie_clk_1]")
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platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks main_clkout_1]")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency (default: 200MHz)")
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parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support")
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parser.add_argument("--driver", action="store_true", help="Generate PCIe driver")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_pcie = args.with_pcie,
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**soc_core_argdict(args)
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)
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builder = Builder(soc, **builder_argdict(args))
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builder.build(run=args.build)
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if args.driver:
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generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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