targets/crosslink_nx: update NXLRAM import.

litex_boards/targets/crosslink_nx_evn.py

@@ -15,7 +15,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex_boards.platforms import crosslink_nx_evn
 
-from litex.soc.cores.nxlram import NXLRAM
+from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.clock import NXPLL
 from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG

litex_boards/targets/crosslink_nx_vip.py

@@ -21,7 +21,7 @@ from litex_boards.platforms import crosslink_nx_vip
 
 from litehyperbus.core.hyperbus import HyperRAM
 
-from litex.soc.cores.nxlram import NXLRAM
+from litex.soc.cores.ram import NXLRAM
 from litex.soc.cores.spi_flash import SpiFlash
 from litex.build.io import CRG
 from litex.build.generic_platform import *