Merge pull request #96 from pepijndevos/oled

Add optional OLED peripheral to ULX3S target
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enjoy-digital 2020-08-04 12:19:58 +02:00 committed by GitHub
commit 623faa9d24
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2 changed files with 31 additions and 0 deletions

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@ -100,6 +100,17 @@ _io = [
Subsignal("pullup", Pins("B12 C12")), Subsignal("pullup", Pins("B12 C12")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("oled_spi", 0,
Subsignal("clk", Pins("P4")),
Subsignal("mosi", Pins("P3")),
IOStandard("LVCMOS33"),
),
("oled_ctl", 0,
Subsignal("dc", Pins("P1")),
Subsignal("resn", Pins("P2")),
Subsignal("csn", Pins("N2")),
IOStandard("LVCMOS33"),
),
] ]
# Platform ----------------------------------------------------------------------------------------- # Platform -----------------------------------------------------------------------------------------

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@ -22,6 +22,8 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import * from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser from litex.soc.cores.led import LedChaser
from litex.soc.cores.spi import SPIMaster
from litex.soc.cores.gpio import GPIOOut
from litedram import modules as litedram_modules from litedram import modules as litedram_modules
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
@ -109,6 +111,20 @@ class BaseSoC(SoCCore):
sys_clk_freq = sys_clk_freq) sys_clk_freq = sys_clk_freq)
self.add_csr("leds") self.add_csr("leds")
def add_oled(self):
pads = self.platform.request("oled_spi")
pads.miso = Signal()
oled = SPIMaster(pads, 8, self.sys_clk_freq, 8e6)
oled.add_clk_divider()
self.submodules.oled_spi = oled
self.add_csr("oled_spi")
ctl_pads = self.platform.request("oled_ctl")
oled_ctl = GPIOOut(ctl_pads)
self.submodules.oled_ctl = oled_ctl
self.add_csr("oled_ctl")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():
@ -121,6 +137,7 @@ def main():
parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-oled", action="store_true", help="Enable SDD1331 OLED support")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
@ -137,6 +154,9 @@ def main():
soc.add_spi_sdcard() soc.add_spi_sdcard()
if args.with_sdcard: if args.with_sdcard:
soc.add_sdcard() soc.add_sdcard()
if args.with_oled:
soc.add_oled()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build) builder.build(**builder_kargs, run=args.build)