Merge pull request #28 from zakgi/master
Adding initial support for Saanlima's Pipistrello LX45 board
This commit is contained in:
enjoy-digital
GitHub
commit
6324433e1c
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.xilinx.programmer import XC3SProg
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from litex.build.openocd import OpenOCD
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_io = [
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("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at hdmi
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("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at hdmi
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("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd
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("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
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("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb
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("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
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("clk50", 0, Pins("H17"), IOStandard("LVTTL")),
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("serial", 0,
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Subsignal("tx", Pins("A10")),
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Subsignal("rx", Pins("A11"), Misc("PULLUP")),
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Subsignal("cts", Pins("C10"), Misc("PULLUP")),
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Subsignal("rts", Pins("A9"), Misc("PULLUP")),
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IOStandard("LVTTL"),
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),
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("usb_fifo", 0,
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Subsignal("data", Pins("A11 A10 C10 A9 B9 A8 B8 A7")),
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Subsignal("rxf_n", Pins("C7")),
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Subsignal("txe_n", Pins("A6")),
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Subsignal("rd_n", Pins("B6")),
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Subsignal("wr_n", Pins("A5")),
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Subsignal("siwua", Pins("C5")),
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IOStandard("LVTTL"),
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),
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("hdmi", 0,
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Subsignal("clk_p", Pins("U5"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("V5"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("T6"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("V6"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("U7"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("V7"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("U8"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("V8"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("V9"), IOStandard("I2C")),
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Subsignal("sda", Pins("T9"), IOStandard("I2C")),
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Subsignal("hpd_notif", Pins("R8"), IOStandard("LVTTL")),
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("mosi", Pins("T13")),
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Subsignal("miso", Pins("R13"), Misc("PULLUP")),
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Subsignal("wp", Pins("T14")),
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Subsignal("hold", Pins("V14")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("spiflash2x", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("dq", Pins("T13 R13"), Misc("PULLUP")),
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Subsignal("wp", Pins("T14")),
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Subsignal("hold", Pins("V14")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("spiflash4x", 0,
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Subsignal("cs_n", Pins("V3")),
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Subsignal("clk", Pins("R15")),
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Subsignal("dq", Pins("T13 R13 T14 V14"), Misc("PULLUP")),
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IOStandard("LVTTL"), Misc("SLEW=FAST")
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),
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("mmc", 0,
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Subsignal("clk", Pins("A3")),
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Subsignal("cmd", Pins("B3"), Misc("PULLUP")),
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Subsignal("dat", Pins("B4 A4 B2 A2"), Misc("PULLUP")),
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IOStandard("SDIO")
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),
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("mmc_spi", 0,
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Subsignal("cs_n", Pins("A2"), Misc("PULLUP")),
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Subsignal("clk", Pins("A3")),
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Subsignal("mosi", Pins("B3")),
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Subsignal("miso", Pins("B4"), Misc("PULLUP")),
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IOStandard("SDIO")
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),
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("audio", 0,
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Subsignal("l", Pins("R7"), Misc("SLEW=SLOW")),
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Subsignal("r", Pins("T7"), Misc("SLEW=SLOW")),
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IOStandard("LVTTL"),
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),
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("pmod", 0,
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Subsignal("d", Pins("D9 C8 D6 C4 B11 C9 D8 C6")),
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IOStandard("LVTTL")
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),
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("ddram_clock", 0,
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Subsignal("p", Pins("G3")),
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Subsignal("n", Pins("G1")),
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IOStandard("MOBILE_DDR")
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),
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("ddram", 0,
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Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
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Subsignal("ba", Pins("F2 F1")),
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Subsignal("cke", Pins("H7")),
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Subsignal("ras_n", Pins("L5")),
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Subsignal("cas_n", Pins("K5")),
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Subsignal("we_n", Pins("E3")),
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Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
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Subsignal("dqs", Pins("L4 P2")),
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Subsignal("dm", Pins("K3 K4")),
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IOStandard("MOBILE_DDR")
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)
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]
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_connectors = [
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("A", "U18 T17 P17 P16 N16 N17 M16 L15 L17 K15 K17 J16 H15 H18 F18 D18"),
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("B", "C18 E18 G18 H16 J18 K18 K16 L18 L16 M18 N18 N15 P15 P18 T18 U17"),
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("C", "F17 F16 E16 G16 F15 G14 F14 H14 H13 J13 G13 H12 K14 K13 K12 L12"),
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]
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_hdmi_infos = {
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"HDMI_OUT0_MNEMONIC": "J4",
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"HDMI_OUT0_DESCRIPTION" : (
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" Type A connector, marked as J4.\\r\\n"
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)
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}
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class Platform(XilinxPlatform):
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name = "pipistrello"
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identifier = 0x5049
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default_clk_name = "clk50"
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default_clk_period = 20
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hdmi_infos = _hdmi_infos
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# Micron N25Q128 (ID 0x0018ba20)
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# FIXME: Create a "spi flash module" object in the same way we have SDRAM
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# module objects.
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spiflash_model = "n25q128"
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spiflash_read_dummy_bits = 10
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spiflash_clock_div = 4
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spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
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spiflash_page_size = 256
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spiflash_sector_size = 0x10000
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# The Pipistrello has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
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# 0x200000 offset (16Mbit) gives plenty of space
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gateware_size = 0x200000
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def __init__(self, programmer="openocd"):
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XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
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self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
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self.programmer = programmer
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def create_programmer(self):
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proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
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if self.programmer == "openocd":
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return OpenOCD(config="board/pipistrello.cfg", flash_proxy_basename=proxy)
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# Alternative programmers - not regularly tested.
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elif self.programmer == "xc3sprog":
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return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")
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else:
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raise ValueError("{} programmer is not supported".format(self.programmer))
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@ -0,0 +1,232 @@
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#!/usr/bin/env python3
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from fractions import Fraction
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import pipistrello
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT46H32M16
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from litedram.phy import s6ddrphy
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from litedram.core import ControllerSettings
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import argparse
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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# Clock domains for the system (soft CPU and related components run at).
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self.clock_domains.cd_sys = ClockDomain()
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# Clock domains for the DDR interface.
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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# Clock domain for peripherals (such as HDMI output).
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self.clock_domains.cd_base50 = ClockDomain()
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self.reset = Signal()
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# Input 50MHz clock
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f0 = 50*1000000
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clk50 = platform.request("clk50")
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clk50a = Signal()
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# Input 50MHz clock (buffered)
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#self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
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clk50b = Signal()
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self.specials += Instance(
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"BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk50, o_DIVCLK=clk50b)
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p = 12
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f = Fraction(clk_freq*p, f0)
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n, d = f.numerator, f.denominator
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assert 19e6 <= f0/d <= 500e6 # pfd
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assert 400e6 <= f0*n/d <= 1080e6 # vco
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# Unbuffered output signals from the PLL. They need to be buffered
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# before feeding into the fabric.
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unbuf_sdram_full = Signal()
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unbuf_sdram_half_a = Signal()
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unbuf_sdram_half_b = Signal()
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unbuf_unused = Signal()
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unbuf_sys = Signal()
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unbuf_periph = Signal()
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# PLL signals
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pll_lckd = Signal()
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pll_fb = Signal()
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self.specials.pll = Instance(
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"PLL_ADV",
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name="crg_pll_adv",
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p_SIM_DEVICE="SPARTAN6", p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01,
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=d,
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# Input Clocks (50MHz)
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i_CLKIN1=clk50b,
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p_CLKIN1_PERIOD=1e9/f0,
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i_CLKIN2=0,
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p_CLKIN2_PERIOD=0.,
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i_CLKINSEL=1,
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# Feedback
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0.,
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# (333MHz) sdram wr rd
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o_CLKOUT0=unbuf_sdram_full, p_CLKOUT0_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4,
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# unused?
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o_CLKOUT1=unbuf_unused, p_CLKOUT1_DUTY_CYCLE=.5,
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=15,
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# (166MHz) sdram_half - sdram dqs adr ctrl
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o_CLKOUT2=unbuf_sdram_half_a, p_CLKOUT2_DUTY_CYCLE=.5,
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p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2,
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# (166MHz) off-chip ddr
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o_CLKOUT3=unbuf_sdram_half_b, p_CLKOUT3_DUTY_CYCLE=.5,
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p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2,
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# ( 50MHz) periph
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o_CLKOUT4=unbuf_periph, p_CLKOUT4_DUTY_CYCLE=.5,
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=20,
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# ( 83MHz) sysclk
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o_CLKOUT5=unbuf_sys, p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1,
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)
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# power on reset?
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reset = platform.request("user_btn") | self.reset
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self.clock_domains.cd_por = ClockDomain()
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por = Signal(max=1 << 11, reset=(1 << 11) - 1)
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self.sync.por += If(por != 0, por.eq(por - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, reset)
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# System clock - 83MHz
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self.specials += Instance("BUFG", i_I=unbuf_sys, o_O=self.cd_sys.clk)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
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# SDRAM clocks
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# ------------------------------------------------------------------------------
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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# sdram_full
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self.specials += Instance("BUFPLL", name="sdram_full_bufpll",
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p_DIVIDE=4,
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i_PLLIN=unbuf_sdram_full, i_GCLK=self.cd_sys.clk,
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i_LOCKED=pll_lckd,
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o_IOCLK=self.cd_sdram_full_wr.clk,
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o_SERDESSTROBE=self.clk4x_wr_strb)
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self.comb += [
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self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
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self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
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]
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# sdram_half
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self.specials += Instance("BUFG", name="sdram_half_a_bufpll", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk)
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clk_sdram_half_shifted = Signal()
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self.specials += Instance("BUFG", name="sdram_half_b_bufpll", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted)
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clk = platform.request("ddram_clock")
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted,
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i_C1=~clk_sdram_half_shifted,
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o_Q=clk.p)
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
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o_Q=clk.n)
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# Peripheral clock - 50MHz
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# ------------------------------------------------------------------------------
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# The peripheral clock is kept separate from the system clock to allow
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# the system clock to be increased in the future.
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dcm_base50_locked = Signal()
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self.specials += [
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Instance("DCM_CLKGEN", name="crg_periph_dcm_clkgen",
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p_CLKIN_PERIOD=20.0,
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p_CLKFX_MULTIPLY=2,
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p_CLKFX_DIVIDE=2,
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p_CLKFX_MD_MAX=1.0, # CLKFX_MULTIPLY/CLKFX_DIVIDE
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p_CLKFXDV_DIVIDE=2,
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p_SPREAD_SPECTRUM="NONE",
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p_STARTUP_WAIT="FALSE",
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i_CLKIN=clk50a,
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o_CLKFX=self.cd_base50.clk,
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o_LOCKED=dcm_base50_locked,
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i_FREEZEDCM=0,
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i_RST=ResetSignal(),
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),
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AsyncResetSynchronizer(self.cd_base50,
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self.cd_sys.rst | ~dcm_base50_locked)
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]
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platform.add_period_constraint(self.cd_base50.clk, 20)
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class BaseSoC(SoCSDRAM):
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mem_map = {
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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}
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mem_map.update(SoCSDRAM.mem_map)
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def __init__(self, **kwargs):
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if 'integrated_rom_size' not in kwargs:
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kwargs['integrated_rom_size']=0x8000
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if 'integrated_sram_size' not in kwargs:
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kwargs['integrated_sram_size']=0x8000
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clk_freq = (83 + Fraction(1, 3))*1000*1000
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platform = pipistrello.Platform()
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SoCSDRAM.__init__(self, platform, clk_freq, **kwargs)
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self.submodules.crg = _CRG(platform, clk_freq)
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self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
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bios_size = 0x8000
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# sdram
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sdram_module = MT46H32M16(self.clk_freq, "1:2")
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self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(
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platform.request("ddram"),
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sdram_module.memtype,
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rd_bitslip=1,
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wr_bitslip=3,
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dqs_ddr_alignment="C1")
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self.add_csr("ddrphy")
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controller_settings = ControllerSettings(with_bandwidth=True)
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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controller_settings=controller_settings)
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
|
||||
|
||||
# Build --------------------------------------------------------------------------------------------
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(description="LiteX SoC on Pipistrello")
|
||||
builder_args(parser)
|
||||
soc_sdram_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = BaseSoC(**soc_sdram_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.build()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue