Add support for QMTech Kintex 7 Development board
This commit is contained in:
Ruurd Keizer
parent
39dc0b36a4
commit
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Kazumoto Kojima
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# Copyright (c) 2023 Ruurd Keizer <ruurdk@hotmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# Clk / Rst
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("clk50", 0, Pins("F22"), IOStandard("LVCMOS33")),
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("cpu_reset", 0, Pins("U26"), IOStandard("LVCMOS33")),
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# Switches
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("sw2", 0, Pins("U26"), IOStandard("LVCMOS33")), # cpu_reset
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("sw3", 0, Pins("V26"), IOStandard("LVCMOS33")),
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# Leds
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("user_led", 0, Pins("R26"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("P26"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("N26"), IOStandard("LVCMOS33")),
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# The board does not have a USB serial connected to the FPGA,
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# so you will have to either connect through the rpi uart through gpio pins (and use serial uart hw or software),
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# or attach an USB to serial adapter on JP5 pins (default)
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("JP5_serial", 0,
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Subsignal("tx", Pins("JP5:7")),
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Subsignal("rx", Pins("JP5:8")),
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IOStandard("LVCMOS33")
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),
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#("gpio_serial", 0,
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# Subsignal("tx", Pins("GPIO:14")),
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# Subsignal("rx", Pins("GPIO:15")),
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# IOStandard("LVCMOS33")
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# )
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# SPIFlash
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# S25FL128L
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("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
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Subsignal("cs_n", Pins("C23")),
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Subsignal("clk", Pins("C8")),
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Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
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IOStandard("LVCMOS33")
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),
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# DDR3 SDRAM
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# MT41J128M16JT-125K
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("ddram", 0,
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Subsignal("a", Pins("AF5 AF2 AD6 AC6 AD4 AB6 AE2 Y5 AA4 AE6 AE3 AD5 AB4 Y6"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("AD3 AE1 AE5"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("AC3"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("AC4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("AF4"), IOStandard("SSTL15")),
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#Subsignal("cs_n", Pins("--"), IOStandard("SSTL15")),
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Subsignal("dm", Pins("V1 V3"), IOStandard("SSTL15")),
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Subsignal("dq", Pins(
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"W1 V2 Y1 Y3 AC2 Y2 AB2 AA3",
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"U1 V4 U6 W3 V6 U2 U7 U5"),
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IOStandard("SSTL15")), # _T_DCI")),
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Subsignal("dqs_p", Pins("AB1 W6"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("dqs_n", Pins("AC1 W5"), IOStandard("DIFF_SSTL15")), # _T_DCI")),
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Subsignal("clk_p", Pins("AA5"), IOStandard("DIFF_SSTL15")),
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Subsignal("clk_n", Pins("AB5"), IOStandard("DIFF_SSTL15")),
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Subsignal("cke", Pins("AD1"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("AF3"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("W4"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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# ("csi", 0,
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# Subsignal("csi", Pins("")),
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# IOStandard("LVCMOS33")
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# ),
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]
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_connectors = [
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# 25x2 header
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("JP5", {
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# odd row even row
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5: "AD21", 6: "AE21",
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7: "AE22", 8: "AF22",
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9: "AE23", 10: "AF23",
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11: "V21", 12: "W21",
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13: "Y22", 14: "AA22",
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15: "AF24", 16: "AF25",
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17: "AB21", 18: "AC21",
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19: "AB22", 20: "AC22",
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21: "AD23", 22: "AD24",
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23: "AC23", 24: "AC24",
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25: "AD25", 26: "AE25",
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27: "AA23", 28: "AB24",
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29: "AA25", 30: "AB25",
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31: "Y23", 32: "AA24",
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33: "AD26", 34: "AE26",
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35: "AB26", 36: "AC26",
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37: "W23", 38: "W24",
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39: "Y25", 40: "Y26",
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41: "W25", 42: "W26",
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43: "V23", 44: "V24",
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45: "U24", 46: "U25",
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}),
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# PMOD_1
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("J11", {
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1: "C16", 7: "B16",
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2: "A17", 8: "B17",
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3: "A18", 9: "A19",
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4: "A20", 10: "B20",
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}),
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# PMOD_2
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("J12", {
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1: "E21", 7: "E22",
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2: "D23", 8: "D24",
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3: "D25", 9: "E25",
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4: "F23", 10: "F24",
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}),
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# PMOD_3
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("J13", {
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1: "A24", 7: "A23",
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2: "B26", 8: "B25",
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3: "D26", 9: "C26",
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4: "F25", 10: "E26",
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}),
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# defining the pins to the rpi's GPIO as virtual connector - signals will still depend on gpio functions
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("GPIO", {
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0: "C12", 1: "B11", 2: "C18", 3: "D18", 4: "E18", 5: "C11", 6: "D10", 7: "B12", 8: "A12", 9: "D14",
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10: "C13", 11: "D13", 12: "A10", 13: "E10", 14: "C17", 15: "A15", 16: "B10", 17: "D16", 18: "B15", 19: "B9",
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20: "A9", 21: "A8", 22: "C14", 23: "A14", 24: "B14", 25: "A13", 26: "C9", 27: "D15",
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})
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 1e9/50e6
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def __init__(self, toolchain="vivado"):
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device = "xc7k325tffg676-1"
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io = _io
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connectors = _connectors
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XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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["write_cfgmem -force -format bin -interface spix4 -size 16 "
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"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
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self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
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self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 33]")
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7k325t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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@ -0,0 +1,223 @@
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2023 Kazumoto Kojima
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# Copyright (c) 2023 Hans Baier <hansfbaier@gmail.com>
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# Copyright (c) 2023 Ruurd Keizer <ruurdk@hotmail.com>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import qmtech_kintex7_devboard
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoVGAPHY
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41J128M16
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from litedram.phy import s7ddrphy
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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if with_ethernet:
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self.clock_domains.cd_eth = ClockDomain()
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if with_vga:
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self.clock_domains.cd_vga = ClockDomain(reset_less=True)
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# # #
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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reset_button = platform.request("cpu_reset")
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self.comb += pll.reset.eq(~reset_button | self.rst)
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pll.register_clkin(platform.request("clk50"), 50e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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pll.create_clkout(self.cd_idelay, 200e6)
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if with_ethernet:
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pll.create_clkout(self.cd_eth, 25e6)
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if with_vga:
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pll.create_clkout(self.cd_vga, 40e6)
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platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6),
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with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
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local_ip="", remote_ip="",
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with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, with_video_colorbars=False,
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with_spi_flash=False, **kwargs):
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platform = qmtech_kintex7_devboard.Platform(toolchain=toolchain)
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# SoCCore ----------------------------------------------------------------------------------
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print(f"{str(kwargs)}")
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if (kwargs["uart_name"] == "serial"):
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kwargs["uart_name"] = "JP5_serial"
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on QMTech Kintex 7 Development board",
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet or with_etherbone, with_video_terminal or with_video_framebuffer or with_video_colorbars)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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from litedram.common import PHYPadsReducer
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram", 0), [0, 1]),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = kwargs.get("l2_size", 8192)
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)
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# Ethernet / Etherbone ---------------------------------------------------------------------
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if with_ethernet or with_etherbone:
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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if with_ethernet:
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self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
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if with_etherbone:
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self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
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# The daughterboard has the tx clock wired to a non-clock pin, so we can't help it
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#self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_clocks_tx_IBUF]")
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self.add_constant("TARGET_BIOS_INIT", 1)
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if local_ip:
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local_ip = local_ip.split(".")
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self.add_constant("LOCALIP1", int(local_ip[0]))
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self.add_constant("LOCALIP2", int(local_ip[1]))
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self.add_constant("LOCALIP3", int(local_ip[2]))
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self.add_constant("LOCALIP4", int(local_ip[3]))
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if remote_ip:
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remote_ip = remote_ip.split(".")
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self.add_constant("REMOTEIP1", int(remote_ip[0]))
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self.add_constant("REMOTEIP2", int(remote_ip[1]))
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self.add_constant("REMOTEIP3", int(remote_ip[2]))
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self.add_constant("REMOTEIP4", int(remote_ip[3]))
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# SPI Flash --------------------------------------------------------------------------------
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if with_spi_flash:
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from litespi.modules import MT25QL128
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x", module=MT25QL128(Codes.READ_1_1_1), with_master=True)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer or with_video_colorbars:
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self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga", format="rgb565")
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if with_video_colorbars:
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self.add_video_colorbars(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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if kwargs["uart_name"] == "serial":
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kwargs["uart_name"] = "jtag_serial"
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on QMTech XC7K325T")
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parser.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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parser.add_argument("--build", action="store_true", help="Build bitstream.")
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parser.add_argument("--load", action="store_true", help="Load bitstream.")
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parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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ethopts = parser.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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parser.add_argument("--remote-ip", default="192.168.1.100",
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help="Remote IP address of TFTP server.")
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parser.add_argument("--local-ip", default="192.168.1.50",
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help="Local IP address.")
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sdopts = parser.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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viopts = parser.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA).")
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viopts.add_argument("--with-video-colorbars", action="store_true", help="Enable Video Colorbars (VGA).")
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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local_ip = args.local_ip,
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remote_ip = args.remote_ip,
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with_spi_flash = args.with_spi_flash,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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with_video_colorbars = args.with_video_colorbars,
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**soc_core_argdict(args)
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)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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if args.with_ethernet or args.with_etherbone:
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os.makedirs(os.path.join(builder.software_dir, "include/generated"),
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exist_ok=True)
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write_to_file(
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os.path.join(builder.software_dir, "include/generated", "target.h"),
|
||||
"// Force 100Base-T speed\n"
|
||||
"#define TARGET_ETHPHY_INIT_FUNC() mdio_write(0, 0, 0x2100)")
|
||||
|
||||
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
|
||||
if args.build:
|
||||
builder.build(**builder_kwargs)
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue