Got HDMI to work on hardware
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Dolu1990
parent
30e26cacac
commit
664525471f
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@ -72,6 +72,16 @@ _bank_info = [
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_connectors = [
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("pmod0", "G15 G16 F16 F17 G17 A11 A13 A12"),
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("pmod1", "B12 C14 C13 C12 D12 F12 D13 E13"),
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("pmod2", "E14 E16 F13 E15 F14 E11 F11 D11"),
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["p1",
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"---", # 0
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# 3V3 5V GND GND GND GND GND GND ↓
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"--- B21 --- A21 --- --- C22 E21 B22 D21 --- --- B23 F21 A22 F22 --- --- D22 G21",
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# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ↑
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# 21 22 23 24 25 26 27 28 28 30 31 32 33 34 35 36 37 38 39 40 ↓
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"D23 G22 --- --- F23 H20 E23 G20 --- --- H22 K23 H23 L23 --- --- L19 M21 M19 M22",
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# GND GND GND GND GND GND ↑
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],
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]
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# PMODS --------------------------------------------------------------------------------------------
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@ -88,6 +98,25 @@ def jtag_pmod_io(pmod):
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IOStandard("3.3_V_LVCMOS")
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),
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]
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def hdmi_px(px):
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return [
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("hdmi_i2c", 0,
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Subsignal("sda", Pins(f"{px}:26")),
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Subsignal("scl", Pins(f"{px}:28")),
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IOStandard("1.8_V_LVCMOS"), Misc("WEAK_PULLUP"), Misc("SCHMITT_TRIGGER")
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),
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("hdmi_data", 0,
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Subsignal("clk", Pins(f"{px}:4")),
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Subsignal("de", Pins(f"{px}:33")),
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Subsignal("d", Pins(f"{px}:31 {px}:27 {px}:25 {px}:21 {px}:19 {px}:15 {px}:13 {px}:9 {px}:7 {px}:2 {px}:8 {px}:10 {px}:14 {px}:16 {px}:20 {px}:22")),
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IOStandard("1.8_V_LVCMOS")
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),
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("hdmi_sync", 0,
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Subsignal("hsync", Pins(f"{px}:37")),
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Subsignal("vsync", Pins(f"{px}:39")),
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IOStandard("1.8_V_LVCMOS")
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(EfinixPlatform):
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@ -20,10 +20,14 @@ from litex.soc.integration.soc import SoCRegion
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect import axi
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from litex.soc.cores.bitbang import I2CMaster
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from liteeth.phy.trionrgmii import LiteEthPHYRGMII
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from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
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from litex.soc.cores.usb_ohci import USBOHCI
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from litex.soc.integration.soc import SoCRegion
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from litex.build.io import DDROutput
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from litex.build.io import SDRTristate
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# python3 -m litex_boards.targets.efinix_ti375_c529_dev_kit --cpu-type=vexiiriscv --cpu-variant=debian --update-repo=no --with-jtag-tap --with-sdcard --with-coherent-dma
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# python3 -m litex.tools.litex_json2dts_linux build/efinix_ti375_c529_dev_kit/csr.json --root-device=mmcblk0p2 > build/efinix_ti375_c529_dev_kit/linux.dts
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@ -35,6 +39,7 @@ class _CRG(LiteXModule):
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#self.rst = Signal()
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self.cd_sys = ClockDomain()
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self.cd_usb = ClockDomain()
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self.cd_video = ClockDomain()
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# # #
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@ -52,6 +57,7 @@ class _CRG(LiteXModule):
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pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="cd_sys_clkout")
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pll.create_clkout(self.cd_usb, 60e6, margin=0)
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pll.create_clkout(None, 800e6, name="dram_clk") # LPDDR4 ctrl
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pll.create_clkout(self.cd_video, 25e6, name ="video_clk")
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -74,9 +80,7 @@ class BaseSoC(SoCCore):
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# OHCI
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if with_ohci:
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from litex.soc.cores.usb_ohci import USBOHCI
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from litex.build.generic_platform import Subsignal, Pins, IOStandard
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from litex.soc.integration.soc import SoCRegion
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_usb_pmod_ios = [
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("usb_pmod1", 0,
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Subsignal("dp", Pins("pmod1:0", "pmod1:1", "pmod1:2", "pmod1:3")),
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@ -109,6 +113,101 @@ class BaseSoC(SoCCore):
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self.comb += jtag_pads.tdo.eq(self.cpu.jtag_tdo)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, jtag_pads.tck)
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_hdmi_io = efinix_ti375_c529_dev_kit.hdmi_px("p1")
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self.platform.add_extension(_hdmi_io)
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self.submodules.videoi2c = I2CMaster(platform.request("hdmi_i2c"))
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self.videoi2c.add_init(addr=0x72>>1, init=[
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# # video input/output mode
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(0xD6, 0xC0),
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(0x15, 0x01),
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(0x16, 0x38),
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(0x18, 0xE7),
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(0x19, 0x34),
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(0x1A, 0x04),
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(0x1B, 0xAD),
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(0x1C, 0x00),
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(0x1D, 0x00),
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(0x1E, 0x1C),
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(0x1F, 0x1B),
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(0x20, 0x1D),
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(0x21, 0xDC),
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(0x22, 0x04),
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(0x23, 0xAD),
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(0x24, 0x1F),
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(0x25, 0x24),
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(0x26, 0x01),
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(0x27, 0x35),
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(0x28, 0x00),
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(0x29, 0x00),
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(0x2A, 0x04),
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(0x2B, 0xAD),
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(0x2C, 0x08),
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(0x2D, 0x7C),
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(0x2E, 0x1B),
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(0x2F, 0x77),
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(0x41, 0x10),
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(0x48, 0x08), # (right justified
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(0x55, 0x00),
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(0x56, 0x28),
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(0x96, 0xC0),
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(0x98, 0x03),
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(0x9A, 0xE0),
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(0x9C, 0x30),
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(0x9D, 0x61),
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(0xA2, 0xA4),
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(0xA3, 0xA4),
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(0xAF, 0x06),
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(0xBA, 0x60),
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(0xD6, 0xC0),
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(0xE0, 0xD0),
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(0xDF, 0x01),
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(0x9A, 0xE0),
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(0xFD, 0xE0),
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(0xFE, 0x80),
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(0xF9, 0x00),
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(0x7F, 0x00),
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(0x94, 0x00),
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(0xE2, 0x01),
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(0x41, 0x10),
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])
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clk_video = self.crg.cd_video.clk
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self.comb += self.cpu.video_clk.eq(self.crg.cd_video.clk)
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video_data = platform.request("hdmi_data")
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self.specials += DDROutput(i1=Signal(reset=0b0), i2=Signal(reset=0b1), o=video_data.clk, clk=clk_video)
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self.specials += DDROutput(i1=self.cpu.video_color_en, i2=self.cpu.video_color_en, o=video_data.de, clk=clk_video)
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for i in range(self.cpu.video_color.nbits):
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self.specials += DDROutput(i1=self.cpu.video_color[i], i2=self.cpu.video_color[i], o=video_data.d[i], clk=clk_video)
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video_sync = platform.request("hdmi_sync")
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self.specials += SDRTristate(io=video_sync.vsync, o=Signal(reset=0b0), oe=self.cpu.video_vsync, i=Signal(), clk=clk_video)
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self.specials += SDRTristate(io=video_sync.hsync, o=Signal(reset=0b0), oe=self.cpu.video_hsync, i=Signal(), clk=clk_video)
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_debug_io = [
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("debug_io", 0,
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Subsignal("p0", Pins("pmod2:0")),
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Subsignal("p1", Pins("pmod2:1")),
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Subsignal("p2", Pins("pmod2:2")),
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Subsignal("p3", Pins("pmod2:3")),
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Subsignal("p4", Pins("pmod2:4")),
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Subsignal("p5", Pins("pmod2:5")),
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Subsignal("p6", Pins("pmod2:6")),
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Subsignal("p7", Pins("pmod2:7")),
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IOStandard("3.3_V_LVCMOS"),
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)
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]
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self.platform.add_extension(_debug_io)
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debug_io = platform.request("debug_io")
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self. comb += debug_io.p0.eq(video_data.clk)
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self. comb += debug_io.p1.eq(self.videoi2c._w.fields.scl)
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self. comb += debug_io.p2.eq(self.videoi2c._r.fields.sda)
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self. comb += debug_io.p3.eq(self.cpu.video_color_en)
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self. comb += debug_io.p4.eq(self.cpu.video_vsync)
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self. comb += debug_io.p5.eq(self.cpu.video_hsync)
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self. comb += debug_io.p6.eq(self.crg.cd_sys.clk)
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self.comb += debug_io.p7.eq(self.crg.cd_sys.clk)
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# LPDDR4 SDRAM -----------------------------------------------------------------------------
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if not self.integrated_main_ram_size:
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# DRAM / PLL Blocks.
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