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litex-boards
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targets: add fixed sdcard clock on boards with SDCard support.

This commit is contained in:
Florent Kermarrec 2020-06-25 11:20:38 +02:00
parent 782c856619
commit 6753a92296
4 changed files with 35 additions and 10 deletions
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8
litex_boards/targets/nexys4ddr.py
View File

@ -30,6 +30,7 @@ class _CRG(Module):
self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain() self.clock_domains.cd_eth = ClockDomain()
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -41,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys2x_dqs, 2*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 50e6) pll.create_clkout(self.cd_eth, 50e6)
pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@ -97,14 +99,18 @@ def main():
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet, with_ethernet=args.with_ethernet,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard: if args.with_spi_sdcard:
soc.add_spi_sdcard() soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)

9
litex_boards/targets/nexys_video.py
View File

@ -30,6 +30,7 @@ class _CRG(Module):
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain() self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -41,6 +42,7 @@ class _CRG(Module):
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6) pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6) pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@ -96,9 +98,16 @@ def main():
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build) builder.build(run=args.build)

12
litex_boards/targets/trellisboard.py
View File

@ -33,7 +33,7 @@ class _CRG(Module):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain() self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_clk10 = ClockDomain() # FIXME: LiteSDCard test self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -55,8 +55,8 @@ class _CRG(Module):
self.submodules.pll = pll = ECP5PLL() self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk12, 12e6) pll.register_clkin(clk12, 12e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6) pll.create_clkout(self.cd_init, 25e6)
pll.create_clkout(self.cd_clk10, 10e6) pll.create_clkout(self.cd_sdcard, 10e6)
self.specials += [ self.specials += [
Instance("ECLKBRIDGECS", Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk, i_CLK0 = self.cd_sys2x_i.clk,
@ -73,9 +73,9 @@ class _CRG(Module):
i_CLKI = self.cd_sys2x.clk, i_CLKI = self.cd_sys2x.clk,
i_RST = self.cd_sys2x.rst, i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk), o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst), AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst), AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | rst),
AsyncResetSynchronizer(self.cd_clk10, ~por_done | ~pll.locked | rst) AsyncResetSynchronizer(self.cd_sdcard, ~por_done | ~pll.locked | rst)
] ]
self.comb += platform.request("dram_vtt_en").eq(1) self.comb += platform.request("dram_vtt_en").eq(1)

16
litex_boards/targets/ulx3s.py
View File

@ -32,6 +32,7 @@ class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False): def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
self.clock_domains.cd_sdcard = ClockDomain()
# # # # # #
@ -45,7 +46,9 @@ class _CRG(Module):
pll.register_clkin(clk25, 25e6) pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) pll.create_clkout(self.cd_sdcard, 10e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
self.specials += AsyncResetSynchronizer(self.cd_sdcard, ~pll.locked | rst)
# USB PLL # USB PLL
if with_usb_pll: if with_usb_pll:
@ -104,8 +107,10 @@ def main():
parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
trellis_args(parser) trellis_args(parser)
@ -115,6 +120,11 @@ def main():
sys_clk_freq=int(float(args.sys_clk_freq)), sys_clk_freq=int(float(args.sys_clk_freq)),
sdram_module_cls=args.sdram_module, sdram_module_cls=args.sdram_module,
**soc_sdram_argdict(args)) **soc_sdram_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build) builder.build(**builder_kargs, run=args.build)