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Merge branch 'master' of https://github.com/machdyne/litex-boards

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inc 2022-07-15 17:13:22 +02:00
commit 67ffe095cc
8 changed files with 34 additions and 18 deletions
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2
litex_boards/platforms/antmicro_datacenter_ddr4_test_board.py
View file

@ -51,8 +51,6 @@ _io = [
Subsignal("act_n", Pins("Y8"), IOStandard("SSTL12_DCI")),
Subsignal("alert_n", Pins("AE10"), IOStandard("SSTL12_DCI")),
Subsignal("par", Pins("AE13"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AF3 AE5 AD6 AC6 AF2 AE3 AE6 AD5"),
IOStandard("SSTL12_DCI")),
Subsignal("dq", Pins(
"W11 Y11 V7 Y7 V11 V9 V8 W8",
"U2 V6 Y2 Y3 U5 U4 W3 Y1",

12
litex_boards/targets/colorlight_5a_75x.py
View file

@ -115,15 +115,15 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False,
def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis", with_ethernet=False,
with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
platform = colorlight_5a_75b.Platform(revision=revision, toolchain=toolchain)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
platform = colorlight_5a_75e.Platform(revision=revision, toolchain=toolchain)
if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
@ -183,6 +183,7 @@ def main():
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (diamond or trellis).")
target_group.add_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
target_group.add_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency")
@ -200,6 +201,7 @@ def main():
soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
@ -209,8 +211,10 @@ def main():
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
if args.build:
builder.build(**trellis_argdict(args))
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer()

9
litex_boards/targets/colorlight_i5.py
View file

@ -94,13 +94,13 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, board="i5", revision="7.0", sys_clk_freq=60e6, with_ethernet=False,
def __init__(self, board="i5", revision="7.0", toolchain="trellis", sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=False, local_ip="", remote_ip="", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
with_video_framebuffer=False, **kwargs):
board = board.lower()
assert board in ["i5", "i9"]
platform = colorlight_i5.Platform(board=board, revision=revision)
platform = colorlight_i5.Platform(board=board, revision=revision, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
@ -180,6 +180,7 @@ def main():
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (diamond or trellis).")
target_group.add_argument("--board", default="i5", help="Board type (i5).")
target_group.add_argument("--revision", default="7.0", type=str, help="Board revision (7.0).")
target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
@ -203,6 +204,7 @@ def main():
args = parser.parse_args()
soc = BaseSoC(board=args.board, revision=args.revision,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
@ -222,8 +224,9 @@ def main():
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
if args.build:
builder.build(**trellis_argdict(args))
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer()

1
litex_boards/targets/fpc_iii.py
View file

@ -143,6 +143,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
**soc_core_argdict(args))

9
litex_boards/targets/lambdaconcept_ecpix5.py
View file

@ -75,14 +75,14 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, device="85F", sys_clk_freq=int(75e6),
def __init__(self, device="85F", sys_clk_freq=int(75e6), toolchain="trellis",
with_ethernet = False,
with_etherbone = False,
with_video_terminal = False,
with_video_framebuffer = False,
with_led_chaser = True,
**kwargs):
platform = lambdaconcept_ecpix5.Platform(device=device, toolchain="trellis")
platform = lambdaconcept_ecpix5.Platform(device=device, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -225,6 +225,7 @@ def main():
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (diamond or trellis).")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
target_group.add_argument("--device", default="85F", help="ECP5 device (45F or 85F).")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
@ -244,6 +245,7 @@ def main():
soc = BaseSoC(
device = args.device,
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_video_terminal = args.with_video_terminal,
@ -253,8 +255,9 @@ def main():
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
if args.build:
builder.build(**trellis_argdict(args))
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer()

9
litex_boards/targets/litex_acorn_baseboard.py
View file

@ -59,7 +59,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6),
def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis",
with_spi_flash = False,
with_ethernet = False,
with_etherbone = False,
@ -67,7 +67,7 @@ class BaseSoC(SoCCore):
with_lcd = False,
with_ws2812 = False,
**kwargs):
platform = litex_acorn_baseboard.Platform(toolchain="trellis")
platform = litex_acorn_baseboard.Platform(toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
@ -124,6 +124,7 @@ def main():
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (diamond or trellis).")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.")
target_group.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
@ -145,6 +146,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
with_spi_flash = args.with_spi_flash,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
@ -158,8 +160,9 @@ def main():
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
if args.build:
builder.build(**trellis_argdict(args))
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer()

9
litex_boards/targets/muselab_icesugar_pro.py
View file

@ -86,11 +86,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=50e6, with_led_chaser=True, with_spi_flash=False,
def __init__(self, sys_clk_freq=50e6, toolchain="trellis", with_led_chaser=True, with_spi_flash=False,
use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
with_video_framebuffer=False, with_ethernet=False, with_etherbone=False,
eth_ip="192.168.1.50", eth_dynamic_ip=False, **kwargs):
platform = muselab_icesugar_pro.Platform()
platform = muselab_icesugar_pro.Platform(toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
with_video_pll = with_video_terminal or with_video_framebuffer
@ -147,6 +147,7 @@ def main():
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build design.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (diamond or trellis).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
@ -170,6 +171,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
with_spi_flash = args.with_spi_flash,
@ -187,8 +189,9 @@ def main():
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
if args.build:
builder.build(**trellis_argdict(args))
builder.build(**builder_kargs)
if args.load:
prog = soc.platform.create_programmer()

1
litex_boards/targets/trellisboard.py
View file

@ -198,6 +198,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
with_ethernet = args.with_ethernet,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,