mirror of
https://github.com/litex-hub/litex-boards.git
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add Linsn RV901T support
This commit is contained in:
Florent Kermarrec
parent
0e4569a48a
commit
684c1640bb
2 changed files with 409 additions and 0 deletions
289
litex_boards/partner/platforms/linsn_rv901t.py
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289
litex_boards/partner/platforms/linsn_rv901t.py
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# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019-2020 Serge Bazanski <serge@bazanski.pl>
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# License: BSD
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# The Linsn RV901T PCB and IOs have been documented with Chubby75 project
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# available at: https://github.com/q3k/chubby75
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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_io = [
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# clock
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("clk25", 0, Pins("M9"), IOStandard("LVCMOS33")),
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# led
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("user_led", 0, Pins("F7"), IOStandard("LVCMOS33")),
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# serial
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("serial", 0,
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Subsignal("tx", Pins("H5")),
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Subsignal("rx", Pins("G6")),
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IOStandard("LVCMOS33")
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),
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# ethernet
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("eth_clocks", 0,
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Subsignal("tx", Pins("D1")),
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Subsignal("rx", Pins("F1")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rx_ctl", Pins("H1")),
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Subsignal("rx_data", Pins("F2 F4 G1 G3")),
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Subsignal("tx_ctl", Pins("E4")),
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Subsignal("tx_data", Pins("E3 E2 E1 F3")),
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IOStandard("LVCMOS33")
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),
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("eth_clocks", 1,
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Subsignal("tx", Pins("J1")),
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Subsignal("rx", Pins("K3")),
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IOStandard("LVCMOS33")
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),
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("eth", 1,
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Subsignal("rx_ctl", Pins("M3")),
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Subsignal("rx_data", Pins("L1 L3 M1 M2")),
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Subsignal("tx_ctl", Pins("H2")),
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Subsignal("tx_data", Pins("J3 K1 K2 H3")),
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IOStandard("LVCMOS33")
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),
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# sdram
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("sdram_clock", 0, Pins("K11"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram_clock", 1, Pins("K12"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("L16 M14 M16 K14 J12 J13 J11 H13 H11 G12 L14")),
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Subsignal("dq", Pins(
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"C15 C16 D14 E15 E16 F14 F16 G14",
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"G11 E12 H14 G16 F15 D16 B16 B15",
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"N16 P16 P15 R15 R16 R14 T14 R12",
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"T12 T13 T15 M13 N14 M15 L12 L13")),
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Subsignal("we_n", Pins("H16")),
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Subsignal("ras_n", Pins("J14")),
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Subsignal("cas_n", Pins("H15")),
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Subsignal("cs_n", Pins("J16")),
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Subsignal("ba", Pins("K16 K15")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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# Direction pin for buffers U600 to U607. 1 is input, 0 is output.
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("bufdir", 0, Pins("F13"), IOStandard("LVCMOS33")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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_connectors = [
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# Lower connector on board. Pin 1 marked with silkscreen layer, pins then
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# alternating through the two rows of the connector.
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("J600", {
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# Buffered through U610, shared with J601
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4: "J6",
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# Buffered through U608, shared with J601
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6: "A11",
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# Buffered through U600
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7: "P4",
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8: "R1",
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9: "M4",
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10: "L5",
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11: "M5",
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12: "K6",
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13: "T4",
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14: "P5",
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# Buffered through U604
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15: "P6",
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16: "M7",
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17: "N6",
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18: "M6",
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19: "L7",
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20: "L8",
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21: "P7",
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22: "N8",
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# Buffered through U601
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23: "M12",
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24: "N11",
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25: "M11",
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26: "M10",
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27: "L10",
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28: "N9",
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29: "P11",
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30: "T11",
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# Buffered through U605
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31: "R9",
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32: "T9",
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33: "T8",
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34: "R7",
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35: "T7",
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36: "T6",
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37: "R5",
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38: "T5",
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# Buffered through U608, shared with J601
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39: "A12",
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40: "B12",
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41: "A13",
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42: "C13",
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43: "A14",
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44: "B14",
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45: "C11",
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# Shared with J601
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47: "E13",
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}),
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# Upper connector on board. Same numbering as J600.
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("J601", {
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# Buffered through U610, shared with J601
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4: "J6",
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# Buffered through U609, shared with J601
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6: "A11",
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# Buffered through U603
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7: "D3",
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8: "C3",
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9: "B3",
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10: "D5",
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11: "A4",
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12: "B2",
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13: "A2",
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14: "A3",
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# Buffered through U607
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15: "A5",
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16: "A6",
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17: "A7",
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18: "A8",
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19: "B8",
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20: "A9",
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21: "A10",
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22: "B10",
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# Buffered through U602
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23: "E11",
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24: "D12",
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25: "D11",
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26: "E10",
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27: "D9",
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28: "F9",
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29: "D8",
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30: "E8",
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# Buffered through U606
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31: "E7",
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32: "D6",
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33: "E6",
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34: "C9",
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35: "C8",
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36: "C7",
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37: "C6",
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38: "B6",
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# Buffered through U609, shared with J600
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39: "A12",
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40: "B12",
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41: "A13",
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42: "C13",
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43: "A14",
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44: "B14",
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45: "C11",
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# Shared with J600
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47: "E13",
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})
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]
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# Extension for HUB75e 'hat' (marked "Huidu Hub75E-10 Support 1/32 ")
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hub75e = [
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("hub75_control", 0,
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# bank select (a, b, c, d, e)
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Subsignal("bank", Pins("J601:42 J601:41 J601:40 J601:39 J600:6")),
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Subsignal("oe", Pins("J600:45")),
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Subsignal("stb", Pins("J601:43")),
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Subsignal("clk", Pins("J601:44")),
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IOStandard("LVCMOS33"),
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),
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# J1
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("hub75_chain", 0,
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Subsignal("r", Pins("J601:38 J601:35")),
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Subsignal("g", Pins("J601:37 J601:34")),
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Subsignal("b", Pins("J601:36 J601:33")),
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IOStandard("LVCMOS33"),
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),
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# J2
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("hub75_chain", 1,
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Subsignal("r", Pins("J601:32 J601:29")),
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Subsignal("g", Pins("J601:31 J601:28")),
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Subsignal("b", Pins("J601:30 J601:27")),
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IOStandard("LVCMOS33"),
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),
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# J3
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("hub75_chain", 2,
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Subsignal("r", Pins("J601:26 J601:23")),
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Subsignal("g", Pins("J601:25 J601:22")),
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Subsignal("b", Pins("J601:24 J601:21")),
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IOStandard("LVCMOS33"),
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),
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# J4
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("hub75_chain", 3,
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Subsignal("r", Pins("J601:20 J601:17")),
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Subsignal("g", Pins("J601:19 J601:16")),
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Subsignal("b", Pins("J601:18 J601:15")),
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IOStandard("LVCMOS33"),
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),
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# J5
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("hub75_chain", 4,
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Subsignal("r", Pins("J601:14 J601:11")),
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Subsignal("g", Pins("J601:13 J601:10")),
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Subsignal("b", Pins("J601:12 J601:9")),
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IOStandard("LVCMOS33"),
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),
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# J6
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("hub75_chain", 5,
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Subsignal("r", Pins("J600:38 J600:35")),
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Subsignal("g", Pins("J600:37 J600:34")),
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Subsignal("b", Pins("J600:36 J600:33")),
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IOStandard("LVCMOS33"),
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),
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# J7
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("hub75_chain", 6,
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Subsignal("r", Pins("J600:32 J600:29")),
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Subsignal("g", Pins("J600:31 J600:28")),
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Subsignal("b", Pins("J600:30 J600:27")),
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IOStandard("LVCMOS33"),
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),
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# J8
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("hub75_chain", 7,
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Subsignal("r", Pins("J600:26 J600:23")),
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Subsignal("g", Pins("J600:25 J600:22")),
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Subsignal("b", Pins("J600:24 J600:21")),
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IOStandard("LVCMOS33"),
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),
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# J9
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("hub75_chain", 8,
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Subsignal("r", Pins("J600:20 J600:17")),
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Subsignal("g", Pins("J600:19 J600:16")),
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Subsignal("b", Pins("J600:18 J600:15")),
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IOStandard("LVCMOS33"),
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),
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# J10
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("hub75_chain", 9,
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Subsignal("r", Pins("J600:14 J600:11")),
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Subsignal("g", Pins("J600:13 J600:10")),
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Subsignal("b", Pins("J600:12 J600:9")),
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IOStandard("LVCMOS33"),
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),
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk25"
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default_clk_period = 1e9/25e6
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors)
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120
litex_boards/partner/targets/linsn_rv901t.py
Executable file
120
litex_boards/partner/targets/linsn_rv901t.py
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@ -0,0 +1,120 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import argparse
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from migen import *
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from litex_boards.platforms import linsn_rv901t
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.clock import S6PLL
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY
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from liteeth.phy.s6rgmii import LiteEthPHYRGMII
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from liteeth.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
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# # #
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clk25 = platform.request("clk25")
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platform.add_period_constraint(clk25, 1e9/25e6)
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self.submodules.pll = pll = S6PLL(speedgrade=-2)
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pll.register_clkin(clk25, 25e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=270)
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
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o_Q=platform.request("sdram_clock"))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCSDRAM):
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def __init__(self, **kwargs):
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platform = linsn_rv901t.Platform()
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sys_clk_freq = int(75e6)
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# SoCSDRAM ---------------------------------------------------------------------------------
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# SDR SDRAM --------------------------------------------------------------------------------
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self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
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sdram_module = M12L64322A(sys_clk_freq, "1:1")
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self.register_sdram(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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mem_map = {
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"ethmac": 0xb0000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, eth_phy=0, **kwargs):
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BaseSoC.__init__(self, **kwargs)
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# Ethernet ---------------------------------------------------------------------------------
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# phy
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy))
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self.add_csr("ethphy")
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# mac
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self.submodules.ethmac = LiteEthMAC(
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phy = self.ethphy,
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dw = 32,
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interface = "wishbone",
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endianness = self.cpu.endianness)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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# timing constraints
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T")
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builder_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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parser.add_argument("--eth-phy", default=0, type=int,
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help="Ethernet PHY 0 or 1 (default=0)")
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args = parser.parse_args()
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if args.with_ethernet:
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soc = EthernetSoC(eth_phy=args.eth_phy, **soc_sdram_argdict(args))
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else:
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soc = BaseSoC(**soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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