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sipeed_tang_meta_138k: Add gowin_ae350 CPU initial support.

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./sipeed_tang_mega_138k.py --cpu-type=gowin_ae350  --build --flash
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Jan 11 2024 12:37:50
 BIOS CRC passed (0efaefbe)

 LiteX git sha1: e689aab1

--=============== SoC ==================--
CPU:		Gowin AE350 @ 800MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX SoC on Tang Mega 138K 2024-01-11 12:37:47
This commit is contained in:
Florent Kermarrec 2024-01-11 13:16:54 +01:00
parent 29143a89f8
commit 688a020f35
1 changed files with 27 additions and 20 deletions
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39
litex_boards/targets/sipeed_tang_mega_138k.py
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@ -4,8 +4,8 @@
# This file is part of LiteX-Boards. # This file is part of LiteX-Boards.
# #
# Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me> # Copyright (c) 2022-2023 Icenowy Zheng <uwu@icenowy.me>
# Copyright (c) 2022 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2022-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr> # Copyright (c) 2023-2024 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import * from migen import *
@ -32,9 +32,11 @@ from litex_boards.platforms import sipeed_tang_mega_138k
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule): class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_ddr3=False, with_video_pll=False): def __init__(self, platform, sys_clk_freq, cpu_clk_freq=0, with_sdram=False, sdram_rate="1:2", with_ddr3=False, with_video_pll=False):
self.rst = Signal() self.rst = Signal()
self.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
if cpu_clk_freq:
self.cd_cpu = ClockDomain()
self.cd_por = ClockDomain() self.cd_por = ClockDomain()
if with_sdram: if with_sdram:
if sdram_rate == "1:2": if sdram_rate == "1:2":
@ -51,21 +53,24 @@ class _CRG(LiteXModule):
self.reset = Signal() self.reset = Signal()
# Clk # Clk
self.clk50 = platform.request("clk50") clk50 = platform.request("clk50")
rst = platform.request("rst") rst = platform.request("rst")
# Power on reset # Power on reset
por_count = Signal(16, reset=2**16-1) por_count = Signal(16, reset=2**16-1)
por_done = Signal() por_done = Signal()
self.comb += self.cd_por.clk.eq(self.clk50) self.comb += self.cd_por.clk.eq(clk50)
self.comb += por_done.eq(por_count == 0) self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1)) self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL # PLL
self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device) self.pll = pll = GW5APLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~por_done | self.rst | rst) self.comb += pll.reset.eq(~por_done | rst)
pll.register_clkin(self.clk50, 50e6) pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=not with_ddr3)
if cpu_clk_freq:
pll.create_clkout(self.cd_cpu, cpu_clk_freq, with_reset=False)
platform.toolchain.additional_cst_commands.append("INS_LOC \"PLL\" PLL_R[0]") # Magic incantation for Gowin-AE350 CPU :)
# SDRAM clock # SDRAM clock
if with_sdram: if with_sdram:
@ -87,10 +92,10 @@ class _CRG(LiteXModule):
i_CEN = self.stop, i_CEN = self.stop,
o_CLKOUT = self.cd_sys2x.clk o_CLKOUT = self.cd_sys2x.clk
), ),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.rst | self.reset), AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
] ]
# Init clock domain # Init clock domain
self.comb += self.cd_init.clk.eq(self.clk50) self.comb += self.cd_init.clk.eq(clk50)
self.comb += self.cd_init.rst.eq(pll.reset) self.comb += self.cd_init.rst.eq(pll.reset)
if with_video_pll: if with_video_pll:
@ -122,17 +127,19 @@ class BaseSoC(SoCCore):
with_rgb_led = False, with_rgb_led = False,
with_buttons = True, with_buttons = True,
**kwargs): **kwargs):
platform = sipeed_tang_mega_138k.Platform(toolchain="gowin") platform = sipeed_tang_mega_138k.Platform(toolchain="gowin")
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq, cpu_clk_freq = int(800e6) if kwargs["cpu_type"] == "gowin_ae350" else 0
self.crg = _CRG(platform, sys_clk_freq, cpu_clk_freq,
with_sdram = with_sdram, with_sdram = with_sdram,
with_ddr3 = with_ddr3, with_ddr3 = with_ddr3,
with_video_pll = with_video_terminal) with_video_pll = with_video_terminal,
)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs) SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Mega 138K", **kwargs)
if cpu_clk_freq:
self.add_config("CPU_CLK_FREQ", cpu_clk_freq)
# DDR3 SDRAM ------------------------------------------------------------------------------- # DDR3 SDRAM -------------------------------------------------------------------------------
if with_ddr3 and not self.integrated_main_ram_size: if with_ddr3 and not self.integrated_main_ram_size:
@ -171,14 +178,14 @@ class BaseSoC(SoCCore):
pads = self.platform.request("eth"), pads = self.platform.request("eth"),
tx_delay = 2e-9, tx_delay = 2e-9,
rx_delay = 2e-9) rx_delay = 2e-9)
self.clk50_half = Signal() clk50_half = Signal()
self.specials += Instance("CLKDIV", self.specials += Instance("CLKDIV",
p_DIV_MODE = "2", p_DIV_MODE = "2",
i_HCLKIN = self.crg.clk50, i_HCLKIN = self.crg.clk50,
i_RESETN = 1, i_RESETN = 1,
i_CALIB = 0, i_CALIB = 0,
o_CLKOUT = self.clk50_half) o_CLKOUT = clk50_half)
self.specials += DDROutput(1, 0, platform.request("ephy_clk"), self.clk50_half) self.specials += DDROutput(1, 0, platform.request("ephy_clk"), clk50_half)
if with_ethernet: if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, data_width=32, software_debug=True) self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip, data_width=32, software_debug=True)
if with_etherbone: if with_etherbone: