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targets: Remove spiflash mapping on targets where it's no longer useful.

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This commit is contained in:
Florent Kermarrec 2021-09-14 18:35:13 +02:00
parent db91eda899
commit 68fb163a27
8 changed files with 0 additions and 8 deletions
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1
litex_boards/targets/alchitry_au.py
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@ -53,7 +53,6 @@ class CRG(Module):
# BaseSoC -----------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, variant="au", sys_clk_freq=int(83333333), with_spi_flash=False, with_led_chaser=True, **kwargs):
platform = alchitry_au.Platform(variant=variant)

1
litex_boards/targets/colorlight_i5.py
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@ -97,7 +97,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0xd0000000}}
def __init__(self, board="i5", revision="7.0", sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=False, local_ip="", remote_ip="", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,

1
litex_boards/targets/digilent_arty.py
View file

@ -57,7 +57,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, variant="a7-35", toolchain="vivado", sys_clk_freq=int(100e6),
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50",
eth_dynamic_ip=False, ident_version=True, with_led_chaser=True, with_jtagbone=True,

1
litex_boards/targets/digilent_arty_s7.py
View file

@ -51,7 +51,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, variant="s7-50", sys_clk_freq=int(100e6), with_spi_flash=False, with_led_chaser=True, **kwargs):
platform = arty_s7.Platform(variant=variant)

1
litex_boards/targets/gsd_butterstick.py
View file

@ -90,7 +90,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, revision="1.0", device="25F", sys_clk_freq=int(60e6), toolchain="trellis",
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_spi_flash=False,

1
litex_boards/targets/muselab_icesugar_pro.py
View file

@ -87,7 +87,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0xd0000000}}
def __init__(self, sys_clk_freq=60e6, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", with_video_terminal=False,
with_video_framebuffer=False, **kwargs):

1
litex_boards/targets/qmtech_xc7a35t.py
View file

@ -69,7 +69,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_daughterboard=False,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,

1
litex_boards/targets/radiona_ulx3s.py
View file

@ -90,7 +90,6 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1",
with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False,