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de10nano/MiSTer: rename SPI SD CARD pins to spisdcard and remove SPI SD Card integration from target.

This commit is contained in:
Florent Kermarrec 2020-03-19 11:09:48 +01:00
parent db9d5489ec
commit 6ab13a0661
2 changed files with 5 additions and 15 deletions
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5
litex_boards/platforms/de10nano.py
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@ -102,9 +102,8 @@ _mister_sdram_module_io = [
IOStandard("3.3-V LVTTL") IOStandard("3.3-V LVTTL")
), ),
# SPI SD CARD HARDWARE BITBANGING ("spisdcard", 0,
("spi",0, Subsignal("clk", Pins("AH26")),
Subsignal("clk", Pins("AH26")),
Subsignal("mosi", Pins("AF27")), Subsignal("mosi", Pins("AF27")),
Subsignal("cs_n", Pins("AF28")), Subsignal("cs_n", Pins("AF28")),
Subsignal("miso", Pins("AF25")), Subsignal("miso", Pins("AF25")),

9
litex_boards/targets/de10nano.py
View File

@ -17,9 +17,6 @@ from litex.soc.integration.builder import *
from litedram.modules import AS4C16M16 from litedram.modules import AS4C16M16
from litedram.phy import GENSDRPHY from litedram.phy import GENSDRPHY
#SPI SD CARD HARDWARE BITBANGING
from litex.soc.cores.spi import SPIMaster
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
@ -106,12 +103,6 @@ class MiSTerSDRAMSoC(SoCSDRAM):
geom_settings = sdram_module.geom_settings, geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings) timing_settings = sdram_module.timing_settings)
# SPI SDCARD HARDWARE BITBANGING
spi_pads = self.platform.request("spi")
self.add_csr("spi")
spi_clk_freq = 400e3
self.submodules.spi = SPIMaster(spi_pads, 8, sys_clk_freq, spi_clk_freq)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():