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sipeed_tang_nano_20k: support copackaged SDRAM 

The copackaged SDRAM of GW2AR-18 QN88 package is 8MB size, 32bit DQ
width.

Add support for it.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
This commit is contained in:
Icenowy Zheng 2023-03-13 17:11:06 +08:00
parent 291c43b898
commit 6b8a5d35c0
2 changed files with 39 additions and 1 deletions
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12
litex_boards/platforms/sipeed_tang_nano_20k.py
View File

@ -62,6 +62,18 @@ _io = [
# Buttons. # Buttons.
("btn", 0, Pins("88"), IOStandard("LVCMOS33")), ("btn", 0, Pins("88"), IOStandard("LVCMOS33")),
("btn", 1, Pins("87"), IOStandard("LVCMOS33")), ("btn", 1, Pins("87"), IOStandard("LVCMOS33")),
# SDRAM (embedded in SIP, requires specific IO naming)
("O_sdram_clk", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_cke", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_cs_n", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_cas_n", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_ras_n", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_wen_n", 0, Pins(1), IOStandard("LVCMOS33")),
("O_sdram_dqm", 0, Pins(4), IOStandard("LVCMOS33")),
("O_sdram_addr", 0, Pins(11), IOStandard("LVCMOS33")),
("O_sdram_ba", 0, Pins(2), IOStandard("LVCMOS33")),
("IO_sdram_dq", 0, Pins(32), IOStandard("LVCMOS33")),
] ]
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------

28
litex_boards/targets/sipeed_tang_nano_20k.py
View File

@ -21,6 +21,9 @@ from litex.soc.integration.builder import *
from litex.soc.cores.gpio import GPIOIn from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.led import LedChaser, WS2812 from litex.soc.cores.led import LedChaser, WS2812
from litedram.modules import M12L64322A # FIXME: use the real model number
from litedram.phy import GENSDRPHY
from litex_boards.platforms import sipeed_tang_nano_20k from litex_boards.platforms import sipeed_tang_nano_20k
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
@ -66,7 +69,30 @@ class BaseSoC(SoCCore):
# TODO: XTX SPI Flash # TODO: XTX SPI Flash
# TODO: copackaged SDRAM # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
class SDRAMPads:
def __init__(self):
self.clk = platform.request("O_sdram_clk")
self.cke = platform.request("O_sdram_cke")
self.cs_n = platform.request("O_sdram_cs_n")
self.cas_n = platform.request("O_sdram_cas_n")
self.ras_n = platform.request("O_sdram_ras_n")
self.we_n = platform.request("O_sdram_wen_n")
self.dm = platform.request("O_sdram_dqm")
self.a = platform.request("O_sdram_addr")
self.ba = platform.request("O_sdram_ba")
self.dq = platform.request("IO_sdram_dq")
sdram_pads = SDRAMPads()
self.specials += DDROutput(0, 1, sdram_pads.clk, ClockSignal("sys"))
self.sdrphy = GENSDRPHY(sdram_pads, sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L64322A(sys_clk_freq, "1:1"), # FIXME.
l2_cache_size = 128,
)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser: