targets/efinix_trion_t120_bga576: Switch to SoCCore (with CPU) and use button as reset (and AsyncResetSynchronizer).
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@ -10,6 +10,7 @@
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import argparse
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import argparse
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from migen import *
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit
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from litex_boards.platforms import efinix_trion_t120_bga576_dev_kit
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@ -26,8 +27,10 @@ class _CRG(Module):
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# # #
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# # #
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clk40 = platform.request("clk40")
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clk40 = platform.request("clk40")
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rst_n = platform.request("user_btn", 0)
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self.comb += self.cd_sys.clk.eq(clk40)
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self.comb += self.cd_sys.clk.eq(clk40)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
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# BaseSoC ------------------------------------------------------------------------------------------
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# BaseSoC ------------------------------------------------------------------------------------------
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@ -35,9 +38,10 @@ class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(40e6), with_led_chaser=True, **kwargs):
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def __init__(self, sys_clk_freq=int(40e6), with_led_chaser=True, **kwargs):
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platform = efinix_trion_t120_bga576_dev_kit.Platform()
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platform = efinix_trion_t120_bga576_dev_kit.Platform()
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# SoCMini ----------------------------------------------------------------------------------
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# SoCCore ----------------------------------------------------------------------------------
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kwargs["with_uart"] = False
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kwargs["integrated_rom_no_we"] = True # FIXME: Avoid this.
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SoCMini.__init__(self, platform, sys_clk_freq,
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kwargs["integrated_sram_no_we"] = True # FIXME: Avoid this.
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SoCCore.__init__(self, platform, sys_clk_freq,
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ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
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ident = "LiteX SoC on Efinix Trion T120 BGA576 Dev Kit",
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ident_version = True,
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ident_version = True,
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**kwargs)
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**kwargs)
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