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sipeed_tang_primer_20k: Disable L2 cache to ease debug and add WIP status.

This commit is contained in:
Florent Kermarrec 2022-09-07 17:07:07 +02:00
parent d39d87b701
commit 6c7157f799
1 changed files with 2 additions and 1 deletions
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litex_boards/targets/sipeed_tang_primer_20k.py
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@ -120,6 +120,7 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Tang Primer 20K", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
# FIXME: WIP.
if not self.integrated_main_ram_size:
self.submodules.ddrphy = GW2DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
@ -131,7 +132,7 @@ class BaseSoC(SoCCore):
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 0)
l2_cache_size = 0
)
# SPI Flash --------------------------------------------------------------------------------