tang nano 4k: add memory regions, set default cpu

This commit is contained in:
Ilia Sergachev 2022-01-23 13:05:51 +01:00
parent e35b9b439f
commit 6c81fc708c
1 changed files with 11 additions and 4 deletions

View File

@ -93,6 +93,15 @@ class BaseSoC(SoCCore):
if self.cpu_type == "gowin_emcu": if self.cpu_type == "gowin_emcu":
self.cpu.connect_uart(platform.request("serial")) self.cpu.connect_uart(platform.request("serial"))
self.bus.add_region("sram", SoCRegion(
origin=self.cpu.mem_map["sram"],
size=16 * 1024)
)
self.bus.add_region("rom", SoCRegion(
origin=self.cpu.mem_map["rom"],
size=32 * 1024,
linker=True)
)
else: else:
# Add ROM linker region -------------------------------------------------------------------- # Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion( self.bus.add_region("rom", SoCRegion(
@ -140,12 +149,9 @@ def main():
parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.") parser.add_argument("--sys-clk-freq",default=27e6, help="System clock frequency.")
builder_args(parser) builder_args(parser)
soc_core_args(parser) soc_core_args(parser)
parser.set_defaults(cpu_type="gowin_emcu")
args = parser.parse_args() args = parser.parse_args()
if args.cpu_type == 'gowin_emcu':
# FIXME: ARM software not supported yet
args.no_compile_software = True
soc = BaseSoC( soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)), sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args) **soc_core_argdict(args)
@ -163,5 +169,6 @@ def main():
prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs")) prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
prog.flash(0, "build/sipeed_tang_nano_4k/software/bios/bios.bin", external=True) prog.flash(0, "build/sipeed_tang_nano_4k/software/bios/bios.bin", external=True)
if __name__ == "__main__": if __name__ == "__main__":
main() main()