commit
6ece97ec59
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@ -121,9 +121,9 @@ def main():
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parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
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parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board")
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parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
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parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
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args = parser.parse_args()
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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sys_clk_freq = int(float(args.sys_clk_freq)),
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