targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.

litex_boards/targets/camlink_4k.py

@@ -68,7 +68,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, toolchain="diamond", **kwargs):
+    def __init__(self, toolchain="trellis", **kwargs):
         platform     = camlink_4k.Platform(toolchain=toolchain)
         sys_clk_freq = int(81e6)
 
@@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
     parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
-        help='gateware toolchain to use, trellis (default) or diamond')
+        help="gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/ecp5_evn.py

@@ -41,7 +41,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs):
         platform = ecp5_evn.Platform(toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -55,8 +55,8 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
-        help='gateware toolchain to use, diamond (default) or  trellis')
+    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
+        help="gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_core_args(parser)
     parser.add_argument("--sys-clk-freq", default=60e6,

litex_boards/targets/hadbadge.py

@@ -72,7 +72,7 @@ class BaseSoC(SoCSDRAM):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge")
     parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
-        help='gateware toolchain to use, trellis (default) or diamond')
+        help="gateware toolchain to use, trellis (default) or diamond")
     parser.add_argument("--sys-clk-freq", default=48e6,
                         help="system clock frequency (default=48MHz)")
     builder_args(parser)

litex_boards/targets/orangecrab.py

@@ -101,7 +101,7 @@ class BaseSoC(SoCSDRAM):
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab")
     parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
-        help="gateware toolchain to use, diamond (default) or  trellis")
+        help="gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)

litex_boards/targets/trellisboard.py

@@ -79,7 +79,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
         platform = trellisboard.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------

litex_boards/targets/versa_ecp5.py

@@ -72,7 +72,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
@@ -102,7 +102,7 @@ class EthernetSoC(BaseSoC):
     }
     mem_map.update(BaseSoC.mem_map)
 
-    def __init__(self, toolchain="diamond", **kwargs):
+    def __init__(self, toolchain="trellis", **kwargs):
         BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
 
         # Ethernet ---------------------------------------------------------------------------------