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added config for ps7; introduced different variants for the zybo-board; fixed pins
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1 changed files with 27 additions and 4 deletions
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@ -5,7 +5,7 @@
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# SPDX-License-Identifier: BSD-2-Clause
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from litex.build.generic_platform import *
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer
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from litex.build.xilinx import Xilinx7SeriesPlatform, VivadoProgrammer, XilinxPlatform
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# IOs ----------------------------------------------------------------------------------------------
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@ -80,22 +80,45 @@ _usb_uart_pmod_io = [
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_connectors = [
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("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
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("pmodb", "T20 U20 V20 W20 Y18 Y19 W18 W19"),
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("pmodb", "V8 W8 U7 V7 Y7 Y6 V6 W6"),
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("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
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("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
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("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
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]
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ps7_config = {
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"z7-20" : {
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"PCW_UIPARAM_DDR_PARTNO " : "MT41K256M16 RE-125",
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"PCW_FPGA_FCLK0_ENABLE " : "1",
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"PCW_UART1_BAUD_RATE " : "115200",
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"PCW_EN_UART1 " : "1",
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"PCW_UART1_PERIPHERAL_ENABLE " : "1",
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"PCW_UART1_UART1_IO " : "MIO 48 .. 49",
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"PCW_PRESET_BANK1_VOLTAGE " : "LVCMOS 1.8V",
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"PCW_USE_M_AXI_GP0 " : "1",
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"PCW_USE_S_AXI_GP0 " : "1",
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"PCW_USB0_PERIPHERAL_ENABLE " : "1",
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"PCW_USB0_USB0_IO " : "MIO 28 .. 39",
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"PCW_USB0_RESET_ENABLE " : "1",
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"PCW_USB0_RESET_IO " : "MIO 46",
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"PCW_EN_USB0 " : "1"
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}
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}
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# Platform -----------------------------------------------------------------------------------------
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class Platform(Xilinx7SeriesPlatform):
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default_clk_name = "clk125"
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default_clk_period = 1e9/125e6
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def __init__(self, toolchain="vivado"):
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Xilinx7SeriesPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain=toolchain)
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def __init__(self, variant="z7-20", toolchain="vivado"):
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device = {
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"z7-10": "xc7z010-clg400-1",
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"z7-20": "xc7z020-clg400-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.add_extension(_ps7_io)
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self.add_extension(_usb_uart_pmod_io)
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self.ps7_config = ps7_config[variant]
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def create_programmer(self):
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return VivadoProgrammer()
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