ecpix5: add DDR3 (working)

litex_boards/platforms/ecpix5.py

@@ -42,6 +42,31 @@ _io = [
         Subsignal("rx", Pins("R26"), IOStandard("LVCMOS33")),
         Subsignal("tx", Pins("R24"), IOStandard("LVCMOS33")),
     ),
+
+    # ddram
+    ("ddram", 0,
+        Subsignal("a", Pins(
+            "T5 M3 L3 V6 K2 W6 K3 L1",
+            "H2 L2 N1 J1 M1 K1"),
+            IOStandard("SSTL15_I")),
+        Subsignal("ba",    Pins("U6 N3 N4"), IOStandard("SSTL15_I")),
+        Subsignal("ras_n", Pins("T3"), IOStandard("SSTL15_I")),
+        Subsignal("cas_n", Pins("P2"), IOStandard("SSTL15_I")),
+        Subsignal("we_n",  Pins("R3"), IOStandard("SSTL15_I")),
+        Subsignal("dm", Pins("U4 U1"), IOStandard("SSTL15_I")),
+        Subsignal("dq", Pins(
+            "T4 W4 R4 W5 R6 P6 P5 P4",
+            "R1 W3 T2 V3 U3 W1 T1 W2",),
+            IOStandard("SSTL15_I"),
+            Misc("TERMINATION=75")),
+        Subsignal("dqs_p", Pins("V4 V1"), IOStandard("SSTL15D_I"),
+            Misc("TERMINATION=OFF"),
+            Misc("DIFFRESISTOR=100")),
+        Subsignal("clk_p", Pins("H3"), IOStandard("SSTL15D_I")),
+        Subsignal("cke",   Pins("P1"), IOStandard("SSTL15_I")),
+        Subsignal("odt",   Pins("P3"), IOStandard("SSTL15_I")),
+        Misc("SLEWRATE=FAST"),
+    ),
 ]
 
 _connectors = []

litex_boards/targets/ecpix5.py

@@ -17,30 +17,59 @@ from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
+from litedram.modules import MT41K256M16
+from litedram.phy import ECP5DDRPHY
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
     def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_init    = ClockDomain()
+        self.clock_domains.cd_por     = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys     = ClockDomain()
+        self.clock_domains.cd_sys2x   = ClockDomain()
+        self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
 
         # # #
 
+        self.stop = Signal()
+
         # Clk / Rst
         clk100 = platform.request("clk100")
         rst_n  = platform.request("rst_n")
         platform.add_period_constraint(clk100, 1e9/100e6)
 
+        # Power on reset
+        por_count = Signal(16, reset=2**16-1)
+        por_done  = Signal()
+        self.comb += self.cd_por.clk.eq(ClockSignal())
+        self.comb += por_done.eq(por_count == 0)
+        self.sync.por += If(~por_done, por_count.eq(por_count - 1))
+
         # PLL
         self.submodules.pll = pll = ECP5PLL()
-
         pll.register_clkin(clk100, 100e6)
-        pll.create_clkout(self.cd_sys, sys_clk_freq)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
+        pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
+        pll.create_clkout(self.cd_init, 25e6)
+        self.specials += [
+            Instance("ECLKSYNCB",
+                i_ECLKI = self.cd_sys2x_i.clk,
+                i_STOP  = self.stop,
+                o_ECLKO = self.cd_sys2x.clk),
+            Instance("CLKDIVF",
+                p_DIV     = "2.0",
+                i_ALIGNWD = 0,
+                i_CLKI    = self.cd_sys2x.clk,
+                i_RST     = self.cd_sys2x.rst,
+                o_CDIVX   = self.cd_sys.clk),
+            AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
+            AsyncResetSynchronizer(self.cd_sys,  ~por_done | ~pll.locked | ~rst_n)
+        ]
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), **kwargs):
         platform = ecpix5.Platform(toolchain="trellis")
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -49,6 +78,29 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # DDR3 SDRAM -------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.ddrphy = ECP5DDRPHY(
+                platform.request("ddram"),
+                sys_clk_freq=sys_clk_freq)
+            self.add_csr("ddrphy")
+            self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
+            self.add_sdram("sdram",
+                phy                     = self.ddrphy,
+                module                  = MT41K256M16(sys_clk_freq, "1:2"),
+                origin                  = self.mem_map["main_ram"],
+                size                    = kwargs.get("max_sdram_size", 0x40000000),
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
+                l2_cache_reverse        = True
+            )
+
+        # Leds (Disable...) ------------------------------------------------------------------------
+        for i in range(4):
+            rgb_led_pads = platform.request("rgb_led", i)
+            for c in "rgb":
+                self.comb += getattr(rgb_led_pads, c).eq(1)
+
 # Load ---------------------------------------------------------------------------------------------
 
 def load():