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litex-boards
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Fix format

This commit is contained in:
Antoni Pokusinski 2023-02-15 11:45:42 +01:00 committed by Tomasz Michalak
parent 0c774a906d
commit 70f2fd6368
2 changed files with 26 additions and 24 deletions
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1
litex_boards/platforms/antmicro_sdi_mipi_video_converter.py
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@ -62,7 +62,6 @@ class Platform(LatticePlatform):
if prog == "ecpprog":
return EcpprogProgrammer()
xcf_template_direct = """<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="R1.2.0">

13
litex_boards/targets/antmicro_sdi_mipi_video_converter.py
View File

@ -15,7 +15,6 @@ import litex_boards.platforms.antmicro_sdi_mipi_video_converter
from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.clock import NXPLL
from litex.build.io import CRG
from litex.build.generic_platform import *
from litex.soc.cores.clock import *
@ -67,7 +66,8 @@ class BaseSoC(SoCCore):
}
def __init__(self, sys_clk_freq=int(75e6), device="LIFCL-40-9BG256C", toolchain="radiant", with_led_chaser=True, **kwargs):
platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform(device=device, toolchain=toolchain)
platform = litex_boards.platforms.antmicro_sdi_mipi_video_converter.Platform(
device=device, toolchain=toolchain)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
@ -76,7 +76,8 @@ class BaseSoC(SoCCore):
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
kwargs["integrated_sram_size"] = 0
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
SoCCore.__init__(self, platform, sys_clk_freq,
ident="LiteX SoC on Crosslink-NX Evaluation Board", **kwargs)
# 128KB LRAM (used as SRAM) ---------------------------------------------------------------
@ -94,6 +95,7 @@ class BaseSoC(SoCCore):
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Crosslink-NX Eval Board")
@ -127,7 +129,8 @@ def main():
if args.load:
prog = soc.platform.create_programmer(args.prog_target, args.programmer)
if args.programmer == "ecpprog" and args.prog_target == "flash":
prog.flash(address=args.address, bitstream=builder.get_bitstream_filename(mode="sram"))
prog.flash(address=args.address,
bitstream=builder.get_bitstream_filename(mode="sram"))
else:
if args.programmer == "radiant":
os.system("sudo modprobe -rf ftdi_sio")
@ -137,6 +140,6 @@ def main():
if args.programmer == "radiant":
os.system("sudo modprobe ftdi_sio")
if __name__ == "__main__":
main()