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Merge pull request #64 from david-sawatzke/improve_colorlight_v6.1 

Improve compatability with colorlight 5a-75b v6.1
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enjoy-digital 2020-04-09 08:05:23 +02:00 committed by GitHub
parent a80737e8b4 15a27d40fa
commit 7157b40718
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2 changed files with 14 additions and 4 deletions
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16
litex_boards/platforms/colorlight_5a_75b.py
View File

@ -19,6 +19,15 @@ _io_v6_1 = [ # Documented by @smunaut
# btn # btn
("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")), ("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")),
# serial
("serial", 0,
Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-)
Subsignal("rx", Pins("R16")), # btn (J19 KEY+)
# It seems there's some capacitance on the KEY+ pin, so bigger baudrates
# may not work
IOStandard("LVCMOS33")
),
# spi flash (GD25Q16CSIG) # spi flash (GD25Q16CSIG)
("spiflash", 0, ("spiflash", 0,
Subsignal("cs_n", Pins("R2")), Subsignal("cs_n", Pins("R2")),
@ -33,7 +42,7 @@ _io_v6_1 = [ # Documented by @smunaut
("sdram", 0, ("sdram", 0,
Subsignal("a", Pins( Subsignal("a", Pins(
"B13 C14 A16 A17 B16 B15 A14 A13", "B13 C14 A16 A17 B16 B15 A14 A13",
"A12 A11 B12 A11")), "A12 A11 B12")),
Subsignal("dq", Pins( Subsignal("dq", Pins(
"D15 E14 E13 D12 E12 D11 C10 B17", "D15 E14 E13 D12 E12 D11 C10 B17",
"B8 A8 C7 A7 A6 B6 A5 B5", "B8 A8 C7 A7 A6 B6 A5 B5",
@ -44,6 +53,7 @@ _io_v6_1 = [ # Documented by @smunaut
Subsignal("cas_n", Pins("A9")), Subsignal("cas_n", Pins("A9")),
#Subsignal("cs_n", Pins("")), # gnd #Subsignal("cs_n", Pins("")), # gnd
#Subsignal("cke", Pins("")), # 3v3 #Subsignal("cke", Pins("")), # 3v3
Subsignal("ba", Pins("B11")), # sdram pin a11 is ba
#Subsignal("dm", Pins("")), # gnd #Subsignal("dm", Pins("")), # gnd
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
Misc("SLEWRATE=FAST") Misc("SLEWRATE=FAST")
@ -67,8 +77,8 @@ _io_v6_1 = [ # Documented by @smunaut
), ),
("eth_clocks", 1, ("eth_clocks", 1,
Subsignal("tx", Pins("")), Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("")), Subsignal("rx", Pins("L19")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33")
), ),
("eth", 1, ("eth", 1,

2
litex_boards/targets/colorlight_5a_75b.py
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@ -7,7 +7,7 @@
# #
# 1) SoC with regular UART and optional Ethernet connected to the CPU: # 1) SoC with regular UART and optional Ethernet connected to the CPU:
# Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+. # Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+.
# ./colorlight_5a_75b.py (add --with-ethernet to add Ethernet capability) # ./colorlight_5a_75b.py --uart-baudrate 9600 (add --with-ethernet to add Ethernet capability)
# ./colorlight_5a_75b.py --load # ./colorlight_5a_75b.py --load
# You should see the LiteX BIOS and be able to interact with it. # You should see the LiteX BIOS and be able to interact with it.
# #