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sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.

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This commit is contained in:
Florent Kermarrec 2021-09-20 08:40:19 +02:00
parent a5c5ba7652
commit 7161ad18ec
1 changed files with 8 additions and 3 deletions
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11
litex_boards/targets/sipeed_tang_nano_4k.py
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@ -12,6 +12,7 @@ import argparse
from migen import * from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock.gowin_gw1nsr import GW1NSRPLL
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
@ -29,15 +30,19 @@ mB = 1024*kB
class _CRG(Module): class _CRG(Module):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq):
self.rst = Signal() self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys = ClockDomain()
# # # # # #
# Clk / Rst # Clk / Rst
clk27 = platform.request("clk27") clk27 = platform.request("clk27")
rst_n = platform.request("user_btn", 0) rst_n = platform.request("user_btn", 0)
self.comb += self.cd_sys.clk.eq(clk27)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) # PLL
self.submodules.pll = pll = GW1NSRPLL(device="GW1NSR-4C")
self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------