Hardware/litex-boards
1
0
Fork 0
mirror of https://github.com/litex-hub/litex-boards.git synced 2025-01-03 03:43:36 -05:00
Code Issues Projects Releases Packages Wiki Activity

sipeed_tang_nano_4k: Integrate new LiteX's GW1NSRPLL.

Browse source
This commit is contained in:
Florent Kermarrec 2021-09-20 08:40:19 +02:00
parent a5c5ba7652
commit 7161ad18ec
1 changed files with 8 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
litex_boards/targets/sipeed_tang_nano_4k.py
View file

@ -12,6 +12,7 @@ import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock.gowin_gw1nsr import GW1NSRPLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
@ -36,8 +37,12 @@ class _CRG(Module):
# Clk / Rst
clk27 = platform.request("clk27")
rst_n = platform.request("user_btn", 0)
self.comb += self.cd_sys.clk.eq(clk27)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
# PLL
self.submodules.pll = pll = GW1NSRPLL(device="GW1NSR-4C")
self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------