axau15: added more FMC+ pins and made some corrrections
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@ -150,22 +150,40 @@ _connectors = [
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"CLK0_P" : "T25",
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"CLK1_N" : "AC21",
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"CLK1_P" : "AB21",
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"DP0_M2C_P" : "Y2",
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"DP0_M2C_N" : "Y1",
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"DP1_M2C_P" : "V2",
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"DP1_M2C_N" : "V1",
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"DP2_M2C_P" : "T2",
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"DP2_M2C_N" : "T1",
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"DP3_M2C_P" : "P2",
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"DP3_M2C_N" : "P1",
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"DP4_M2C_P" : "M2",
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"DP4_M2C_N" : "M1",
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"DP5_M2C_P" : "K2",
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"DP5_M2C_N" : "K1",
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"DP6_M2C_P" : "H2",
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"DP6_M2C_N" : "H1",
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"DP7_M2C_P" : "F2",
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"DP7_M2C_N" : "F1",
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"DP0_C2M_P" : "AA5",
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"DP0_C2M_N" : "AA4",
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"DP1_C2M_P" : "W5",
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"DP1_C2M_N" : "W4",
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"DP2_C2M_P" : "U5",
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"DP2_C2M_N" : "U4",
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"DP3_C2M_P" : "R5",
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"DP3_C2M_N" : "R4",
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"DP0_C2M_P" : "AA5",
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"DP0_C2M_N" : "AA4",
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"DP0_M2C_P" : "Y2",
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"DP0_M2C_N" : "Y1",
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"DP4_C2M_P" : "N5",
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"DP4_C2M_N" : "N4",
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"DP5_C2M_P" : "L5",
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"DP5_C2M_N" : "L4",
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"DP6_C2M_P" : "J5",
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"DP6_C2M_N" : "J4",
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"DP7_C2M_P" : "G5",
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"DP7_C2M_N" : "G4",
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"LA06_P" : "N23",
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"LA06_N" : "P23",
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"LA10_P" : "W25",
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@ -56,7 +56,7 @@ class BaseSoC(SoCCore):
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with_etherbone = False,
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eth_ip = "192.168.1.50",
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with_led_chaser = True,
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with_pcie = True,
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with_pcie = False,
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**kwargs):
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platform = alinx_axau15.Platform()
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@ -145,7 +145,6 @@ def main():
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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# TODO: add option for FrontPanel Programming
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if __name__ == "__main__":
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main()
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