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xu8_pe3: Fix clk_p/n on pcie_x8.

This commit is contained in:
Florent Kermarrec 2023-07-13 18:10:46 +02:00
parent 18a3909a9c
commit 72a951081a
1 changed files with 2 additions and 2 deletions
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4
litex_boards/platforms/enclustra_mercury_xu8_pe3.py
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@ -54,8 +54,8 @@ _io = [
("pcie_x8", 0, # GTH Bank 227 and 226.
Subsignal("rst_n", Pins("AF2"), IOStandard("LVCMOS12"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("H10")),
Subsignal("clk_n", Pins("H9")),
Subsignal("clk_p", Pins("B10")),
Subsignal("clk_n", Pins("B9")),
Subsignal("rx_p", Pins("D2 C4 B2 A4 H2 G4 F2 E4")),
Subsignal("rx_n", Pins("D1 C3 B1 A3 H1 G3 F1 E3")),
Subsignal("tx_p", Pins("D6 C8 B6 A8 H6 G8 F6 E8")),