targets: create platform on BaseSoC for all targets (consitency).

litex_boards/targets/aller.py

@@ -56,7 +56,8 @@ class CRG(Module):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, with_pcie=False, **kwargs):
+    def __init__(self, with_pcie=False, **kwargs):
+        platform = aller.Platform()
         sys_clk_freq = int(100e6)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -112,9 +113,8 @@ def main():
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    platform = aller.Platform()
-    soc      = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
-    builder  = Builder(soc, **builder_argdict(args))
+    soc     = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
     if args.driver:

litex_boards/targets/crosslink_nx_evn.py

@@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
     }
     def __init__(self, sys_clk_freq, **kwargs):
         platform = crosslink_nx_evn.Platform()
-
         platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
 
         # Disable Integrated SRAM since we want to instantiate LRAM specifically for it

litex_boards/targets/crosslink_nx_vip.py

@@ -69,7 +69,6 @@ class BaseSoC(SoCCore):
     }
     def __init__(self, sys_clk_freq, hyperram="none", **kwargs):
         platform = crosslink_nx_vip.Platform()
-
         platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
 
         # Disable Integrated SRAM since we want to instantiate LRAM specifically for it

litex_boards/targets/nereid.py

@@ -53,7 +53,8 @@ class CRG(Module):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, with_pcie=False, **kwargs):
+    def __init__(self, with_pcie=False, **kwargs):
+        platform = nereid.Platform()
         sys_clk_freq = int(100e6)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -104,8 +105,7 @@ def main():
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    platform = nereid.Platform()
-    soc      = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
+    soc     = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex_boards/targets/tagus.py

@@ -57,7 +57,8 @@ class CRG(Module):
 # BaseSoC -----------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, with_pcie=False, **kwargs):
+    def __init__(self, with_pcie=False, **kwargs):
+        platform = tagus.Platform()
         sys_clk_freq = int(100e6)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -113,8 +114,7 @@ def main():
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    platform = tagus.Platform()
-    soc      = BaseSoC(platform, with_pcie=args.with_pcie, **soc_sdram_argdict(args))
+    soc     = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex_boards/targets/ulx3s.py

@@ -82,7 +82,6 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
         sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs):
-
         platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------