vc707.py: clk156 add missing constraint

2021-02-08 19:04:01 -08:00 · 2021-02-08 19:04:01 -08:00 · 7442c2dada
parent fef9dd036a
commit 7442c2dada
1 changed files with 1 additions and 0 deletions
--- a/litex_boards/platforms/vc707.py
+++ b/litex_boards/platforms/vc707.py
@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
    def do_finalize(self, fragment):
        XilinxPlatform.do_finalize(self, fragment)
        self.add_period_constraint(self.lookup_request("clk200",      loose=True), 1e9/200e6)
+        self.add_period_constraint(self.lookup_request("clk156",      loose=True), 1e9/156e6)
        self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)