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vc707.py: clk156 add missing constraint

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Michael Betz 2021-02-08 19:04:01 -08:00
parent fef9dd036a
commit 7442c2dada
1 changed files with 1 additions and 0 deletions
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litex_boards/platforms/vc707.py
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@ -642,4 +642,5 @@ class Platform(XilinxPlatform):
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("clk156", loose=True), 1e9/156e6)
self.add_period_constraint(self.lookup_request("sgmii_clock", loose=True), 1e9/125e6)